Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 142  2003-2013 Microchip Technology Inc.
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 6-bit wide port with 5 bidirectional pins and
1 unidirectional pin. The corresponding data direction
register is TRISG. Setting a TRISG bit (= 1) will make
the corresponding PORTG pin an input (i.e., put the
corresponding output driver in a high-impedance
mode). Clearing a TRISG bit (= 0) will make the corre-
sponding PORTG pin an output (i.e., put the contents
of the output latch on the selected pin).
The Data Latch register (LATG) is also memory mapped.
Read-modify-write operations on the LATG register read
and write the latched output value for PORTG.
Pins RG0-RG2 on PORTG are multiplexed with the CAN
peripheral. Refer to Section 23.0 “ECAN Module” for
proper settings of TRISG when CAN is enabled. RG5 is
multiplexed with MCLR
/VPP. Refer to Register 24-5 for
more information.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
EXAMPLE 10-7: INITIALIZING PORT
FIGURE 10-16: RG0/CANTX1 PIN BLOCK DIAGRAM
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Note 1: On a Power-on Reset, RG5 is enabled as
a digital input only if Master Clear
functionality is disabled (MCLRE = 0).
2: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
(CONFIG4L<2> = 0); or
b) make certain that RB5/KBI1/PGM is
held low during entry into ICSP.
CLRF PORTG ; Initialize PORTG by
; clearing output
; data latches
CLRF LATG ; Alternate method
; to clear output
; data latches
MOVLW 04h ; Value used to
; initialize data
; direction
MOVWF TRISG ; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
Data Latch
TRIS Latch
RD TRISG
P
V
SS
Q
D
Q
CK
Q
D
Q
CK
EN
QD
EN
N
VDD
0
1
RD PORTG
WR TRISG
Data Bus
I/O pin
TXD
ENDRHI
OPMODE2:OPMODE0 = 000
Schmitt
Trigger
RD LATG
WR PORTG or
WR LATG
OPMODE2:OPMODE0 = 000
Note: I/O pins have diode protection to VDD and VSS.
18F8680.book Page 142 Tuesday, January 29, 2013 1:32 PM