Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 121
PIC18F6585/8585/6680/8680
REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
—CMIP— EEIP BCLIP LVDIP TMR3IP CCP2IP
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
18F8680.book Page 121 Tuesday, January 29, 2013 1:32 PM