Datasheet

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PIC18F8723 Family

Data Sheet

64/80-Pin, 1-Mbit,

Enhanced Flash Microcontrollers

with 12-Bit A/D and nanoWatt Technology

Summary of content (60 pages)

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PIC18F8723 Family Data Sheet 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology © 2009 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC18F8723 FAMILY 64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology Peripheral Highlights: Power-Managed Modes: • 12-Bit, Up to 16-Channel Analog-to-Digital Converter module (A/D): - Auto-acquisition capability - Conversion available during Sleep • Two Master Synchronous Serial Port (MSSP) modules supporting 2/3/4-Wire SPI (all four modes) and I2C™ Master and Slave modes • Two Capture/Compare/PWM (CCP) modules • Three Enhanced Capture/Compare/PWM (ECCP) modules: -
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PIC18F8723 Pin Diagrams RD7/PSP7/SS2 RD6/PSP6/SCK2/SCL2 RD5/PSP5/SDI2/SDA2 RD4/PSP4/SDO2 RD3/PSP3 RD2/PSP2 RD1/PSP1 VSS VDD RD0/PSP0 RE7/ECCP2(1)/P2A(1) RE6/P1B RE5/P1C RE4/P3B RE2/CS/P2B RE3/P3C 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR/P2C RE0/RD/P2D RG0/ECCP3/P3A RG1/TX2/CK2 RF4/AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RF3/AN8 RF2/AN7/C1OUT 15 16 RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR/VPP RG4/CCP5/P1D VSS VDD RF7/SS1 RF6/AN11 RF5/AN10/CVREF 48 47 46 45 44 43 42 41
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PIC18F8723 Pin Diagrams (Continued) RH1/A17 RH0/A16 RE2/AD10/CS/P2B RE3/AD11/P3C(2) RE4/AD12/P3B(2) RE5/AD13/P1C(2) RE6/AD14/P1B(2) RE7/AD15/ECCP2(1)/P2A(1) RD0/AD0/PSP0 VDD VSS RD1/AD1/PSP1 RD2/AD2/PSP2 RD3/AD3/PSP3 RD4/AD4/PSP4/SDO2 RD5/AD5/PSP5/SDI2/SDA2 RD6/AD6/PSP6/SCK2/SCL2 RD7/AD7/PSP7/SS2 RJ0/ALE RJ1/OE 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18 RH3/A19 RE1/AD9/WR/P2C RE0/AD8/RD/P2D RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D RG5/MCLR/VPP RG4/CCP5/P1D V
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PIC18F8723 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 31 3.0 Special Features of the CPU ...................................................................................
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PIC18F8723 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
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PIC18F8723 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F6628 • PIC18LF6628 • PIC18F6723 • PIC18LF6723 • PIC18F8628 • PIC18LF8628 • PIC18F8723 • PIC18LF8723 Note: This data sheet documents only the devices’ features and specifications that are in addition to the features and specifications of the PIC18F8722 family devices.
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PIC18F8723 FAMILY TABLE 1-1: DEVICE FEATURES Features PIC18F6628 PIC18F6723 PIC18F8628 PIC18F8723 Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz 96K 128K 96K 128K Program Memory (Instructions) 49152 65536 49152 65536 Data Memory (Bytes) 3936 3936 3936 3936 Data EEPROM Memory (Bytes) 1024 1024 1024 1024 28 28 29 29 Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J Timers 5 5 5 5
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PIC18F8723 FAMILY FIGURE 1-1: PIC18F6628/6723 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch Program Memory (48/64/96/128 Kbytes) STKPTR Instruction Bus <16> PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 12 Data Latch 8 RA0:RA7(1) Data Memory (3.
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PIC18F8723 FAMILY FIGURE 1-2: PIC18F8628/8723 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 inc/dec logic 21 Address Latch PCU PCH PCL Program Counter 31 Level Stack System Bus Interface PORTB RB0:RB7(1) 12 Data Address<12> 4 Address Latch Program Memory (48/64/96/128 Kbytes) RA0:RA7(1) Data Memory (3.
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PIC18F8723 FAMILY TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS Pin Name Pin Number TQFP Buffer Type I I ST ST 7 RG5/MCLR/VPP RG5 MCLR P VPP OSC1/CLKI/RA7 OSC1 Pin Type 39 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 Description Master Clear (input) or programming voltage (input). Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input.
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PIC18F8723 FAMILY TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 T0CKI 28 RA5/AN4/HLVDIN RA5 AN4 HLVDIN 27 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2.
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PIC18F8723 FAMILY TABLE 1-2: Pin Name PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F8723 FAMILY TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/ P2A RC1 T1OSI ECCP2(1) 29 P2A(1) RC2/ECCP1/P1A RC2 ECCP1 I/O O I ST — ST I/O I I/O ST CMOS ST O — I/O I/O ST ST O — Digital I/O. Enhanced Capture 1 input/Compare 1 output/ PWM1 output. ECCP1 PWM output A. I/O I/O I/O ST ST ST Digital I/O.
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PIC18F8723 FAMILY TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/PSP0 RD0 PSP0 58 RD1/PSP1 RD1 PSP1 55 RD2/PSP2 RD2 PSP2 54 RD3/PSP3 RD3 PSP3 53 RD4/PSP4/SDO2 RD4 PSP4 SDO2 52 RD5/PSP5/SDI2/ SDA2 RD5 PSP5 SDI2 SDA2 51 RD6/PSP6/SCK2/ SCL2 RD6 PSP6 SCK2 SCL2 50 RD7/PSP7/SS2 RD7 PSP7 SS2 49 I/O I/O ST TTL Digital I/O. Parallel Slave Port data.
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PIC18F8723 FAMILY TABLE 1-2: Pin Name PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/RD/P2D RE0 RD P2D 2 RE1/WR/P2C RE1 WR P2C 1 RE2/CS/P2B RE2 CS P2B 64 RE3/P3C RE3 P3C 63 RE4/P3B RE4 P3B 62 RE5/P1C RE5 P1C 61 RE6/P1B RE6 P1B 60 RE7/ECCP2/P2A RE7 ECCP2(2) 59 P2A(2) I/O I O ST TTL — Digital I/O. Read control for Parallel Slave Port. ECCP2 PWM output D.
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PIC18F8723 FAMILY TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 18 RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF3 AN8 15 RF4/AN9 RF4 AN9 14 RF5/AN10/CVREF RF5 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS1 RF7 SS1 11 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog — Digital I/O. Analog input 6.
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PIC18F8723 FAMILY TABLE 1-2: PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 3 P3A RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3/CCP4/P3D RG3 CCP4 P3D 6 RG4/CCP5/P1D RG4 CCP5 P1D 8 I/O I/O ST ST O — Digital I/O. Enhanced Capture 3 input/Compare 3 output/ PWM3 output. ECCP3 PWM output A. I/O O I/O ST — ST Digital I/O.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS Pin Name Pin Number TQFP RG5/MCLR/VPP RG5 MCLR I I ST ST P 49 I CLKI I RA7 OSC2/CLKO/RA6 OSC2 Buffer Type 9 VPP OSC1/CLKI/RA7 OSC1 Pin Type I/O Description Master Clear (input) or programming voltage (input). Digital input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Oscillator crystal or external clock input.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 RA1/AN1 RA1 AN1 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/T0CKI RA4 T0CKI 34 RA5/AN4/HLVDIN RA5 AN4 HLVDIN 33 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 36 RC1/T1OSI/ECCP2/ P2A RC1 T1OSI ECCP2(2) 35 P2A(2) RC2/ECCP1/P1A RC2 ECCP1 I/O O I ST — ST I/O I I/O ST CMOS ST O — I/O I/O ST ST O — Digital I/O. Enhanced Capture 1 input/Compare 1 output/ PWM1 output. ECCP1 PWM output A. I/O I/O I/O ST ST ST Digital I/O.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 24 RF1/AN6/C2OUT RF1 AN6 C2OUT 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8 RF3 AN8 17 RF4/AN9 RF4 AN9 16 RF5/AN10/CVREF RF5 AN10 CVREF 15 RF6/AN11 RF6 AN11 14 RF7/SS1 RF7 SS1 13 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog — Digital I/O. Analog input 6.
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PIC18F8723 FAMILY TABLE 1-3: PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 5 P3A RG1/TX2/CK2 RG1 TX2 CK2 6 RG2/RX2/DT2 RG2 RX2 DT2 7 RG3/CCP4/P3D RG3 CCP4 P3D 8 RG4/CCP5/P1D RG4 CCP5 P1D 10 RG5 I/O I/O ST ST O — Digital I/O. Enhanced Capture 3 input/Compare 3 output/ PWM3 output. ECCP3 PWM output A. I/O O I/O ST — ST Digital I/O.
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PIC18F8723 FAMILY TABLE 1-3: Pin Name PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0/A16 RH0 A16 79 RH1/A17 RH1 A17 80 RH2/A18 RH2 A18 1 RH3/A19 RH3 A19 2 RH4/AN12/P3C RH4 AN12 P3C(5) 22 RH5/AN13/P3B RH5 AN13 P3B(5) 21 RH6/AN14/P1C RH6 AN14 P1C(5) 20 RH7/AN15/P1B RH7 AN15 P1B(5) 19 I/O I/O ST TTL Digital I/O. External memory address/data 16. I/O I/O ST TTL Digital I/O.
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PIC18F8723 FAMILY TABLE 1-3: Pin Name PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 62 RJ1/OE RJ1 OE 61 RJ2/WRL RJ2 WRL 60 RJ3/WRH RJ3 WRH 59 RJ4/BA0 RJ4 BA0 39 RJ5/CE RJ4 CE 40 RJ6/LB RJ6 LB 41 RJ7/UB RJ7 UB 42 I/O O ST — Digital I/O. External memory address latch enable. I/O O ST — Digital I/O. External memory output enable. I/O O ST — Digital I/O.
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PIC18F8723 FAMILY 2.0 12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 12 inputs for the 64-pin devices (PIC18F6628/6723) and 16 for the 80-pin devices (PIC18F8628/8723). This module allows conversion of an analog input signal to a corresponding 12-bit digital number. The ADCON0 register, shown in Register 2-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 2-2, configures the functions of the port pins.
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PIC18F8723 FAMILY REGISTER 2-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+
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PIC18F8723 FAMILY REGISTER 2-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110
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PIC18F8723 FAMILY The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ and RA2/AN2/VREF-/CVREF pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input or a digital I/O.
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PIC18F8723 FAMILY Wait for A/D conversion to complete by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. 6. 7.
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PIC18F8723 FAMILY 2.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 2-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
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PIC18F8723 FAMILY 2.2 Selecting and Configuring Acquisition Time 2.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 13 TAD per 12-bit conversion. The source of the A/D conversion clock is software selectable.
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PIC18F8723 FAMILY 2.4 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used. The ACQT2:ACQT0 bits do not need to be adjusted as the ADCS2:ADCS0 bits adjust the TAD time for the new clock speed.
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PIC18F8723 FAMILY 2.6 A/D Conversions After the A/D conversion is completed or aborted, a 2 TCY wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Figure 2-4 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
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PIC18F8723 FAMILY 2.8 Use of the ECCP2 Trigger An A/D conversion can be started by the Special Event Trigger of the ECCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion, and the Timer1 (or Timer3) counter will be reset to zero.
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PIC18F8723 FAMILY 3.0 SPECIAL FEATURES OF THE CPU Note: 3.1 For additional details on the Configuration bits, refer to Section 25.1 “Configuration Bits” in the “PIC18F8722 Family Data Sheet” (DS39646). Device ID information presented in this section is for the PIC18F8723 family only. Device ID Registers The Device ID registers are “read-only” registers. They identify the device type and revision to device programmers and can be read by firmware using table reads.
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PIC18F8723 FAMILY REGISTER 3-1: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F8723 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits See Register 3-2 for a complete listing. bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision.
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PIC18F8723 FAMILY 4.0 ELECTRICAL CHARACTERISTICS Note: Other than some basic data, this section documents only the PIC18F8723 family’s specifications that differ from those of the PIC18F8722 family devices. For detailed information on the electrical specifications shared by the PIC18F8723 family and PIC18F8722 family devices, see the “PIC18F8722 Family Data Sheet” (DS39646). Absolute Maximum Ratings(†) Ambient temperature under bias.........................................................................
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PIC18F8723 FAMILY FIGURE 4-1: PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V PIC18F8723 Family 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20 MHz in 8-Bit External Memory mode. FMAX = 40 MHz in all other modes. FIGURE 4-2: PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F8723 Family 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX Frequency FMAX = 20 MHz in 8-Bit External Memory mode. FMAX = 25 MHz in all other modes.
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PIC18F8723 FAMILY FIGURE 4-3: PIC18LF8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF8723 Family 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX 4 MHz Frequency In 8-Bit External Memory mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V; FMAX = 25 MHz, if VDDAPPMIN > 4.2V. In all other modes: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
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PIC18F8723 FAMILY TABLE 4-1: Param No. A/D CONVERTER CHARACTERISTICS: PIC18F8723 FAMILY (INDUSTRIAL) Sym Characteristic Min Typ Max Units Conditions ΔVREF ≥ 3.0V A01 NR Resolution — — 12 bit A03 EIL Integral Linearity Error — <±1 ±2.0 LSB VDD = 3.0V ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error A06 EOFF Offset Error A07 EGN Gain Error A10 — Monotonicity A20 ΔVREF Reference Voltage Range (VREFH – VREFL) — — ±2.0 LSB VDD = 5.0V — <±1 +1.5/-1.0 LSB VDD = 3.
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PIC18F8723 FAMILY FIGURE 4-4: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 11 A/D DATA 10 9 ... ... 3 2 1 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
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PIC18F8723 FAMILY 5.0 PACKAGING INFORMATION For packaging information, see the “PIC18F8722 Family Data Sheet” (DS39646). © 2009 Microchip Technology Inc.
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PIC18F8723 FAMILY APPENDIX A: REVISION HISTORY Revision A (August 2007) Original data sheet for the PIC18F8723 family of devices. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (October 2009) Updated to remove Preliminary status.
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PIC18F8723 FAMILY APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39894B-page 52 APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e.
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PIC18F8723 FAMILY APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
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PIC18F8723 FAMILY INDEX A F A/D ...................................................................................... 31 A/D Converter Interrupt, Configuring .......................... 35 Acquisition Requirements ........................................... 36 ADCON0 Register....................................................... 31 ADCON1 Register....................................................... 31 ADCON2 Register....................................................... 31 ADRESH Register............
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PIC18F8723 FAMILY RD1/AD1/PSP1........................................................... 25 RD1/PSP1................................................................... 17 RD2/AD2/PSP2........................................................... 25 RD2/PSP2................................................................... 17 RD3/AD3/PSP3........................................................... 25 RD3/PSP3................................................................... 17 RD4/AD4/PSP4/SDO2 ..............
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PIC18F8723 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC18F8723 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC18F8723 FAMILY PIC18F8723 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device(1) (2) PIC18F6628/6723, PIC18F8628/8723, VDD range 4.2V to 5.5V PIC18LF6628/6723, PIC18LF6628/6723( VDD range 2.0V to 5.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.