Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 9
PIC18F6525/6621/8525/8621
FIGURE 1-1: PIC18F6525/6621 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode and
Control
OSC1/CLKI
OSC2/CLKO
V
DD,
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/LVDIN
RB0/INT0/FLT0
RC0/T1OSO/T13CKI
RC1/T1OSI/ECCP2
(1)
/P2A
(1)
RC2/ECCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
Brown-out
Reset
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
RB1/INT1
Data Latch
Data RAM
(3.8 Kbytes)
Address Latch
Address<12>
12
Bank 0, F
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Decode
4
12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
W
8
BITOP
8
8
ALU<8>
8
Test Mode
Select
Address Latch
Program Memory
(48/64 Kbytes)
Data Latch
20
21
16
8
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD7/PSP7
RB2/INT2
RB3/INT3
PCLATU
PCU
Precision
Reference
Band Gap
PORTE
PORTG
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG4/CCP5/P1D
RE6/P1B
RE7/ECCP2
(1)
/P2A
(1)
RE5/P1C
RE4/P3B
RE3/P3C
RE2/CS/P2B
RE0/RD/P2D
RE1/WR/P2C
OSC2/CLKO/RA6
VSS
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set, or RE7 when CCP2MX is not set.
2: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.
PORTF
RF6/AN11
RF7/SS
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RF0/AN5
RF1/AN6/C2OUT
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR
(2)
MCLR/VPP/RG5
(2)
:RD0/PSP0
EUSART1Comparator
MSSP
EUSART2
10-bit
ADC
Timer2Timer1 Timer3 Timer4Timer0
CCP4 CCP5
LVD
ECCP2 ECCP3 ECCP1
BOR
Data
EEPROM