Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 75
PIC18F6525/6621/8525/8621
6.2.3 16-BIT BYTE SELECT MODE
Figure 6-3 shows an example of 16-bit Byte Select
mode for PIC18F8525/8621 devices. This mode allows
table write operations to word-wide external memories
with byte selection capability. This generally includes
both word-wide Flash and SRAM devices.
During a TBLWT cycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH
signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written based on the Least
Significant bit of the TBLPTR register.
Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB
or LB signals to select the byte.
FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE
AD<7:0>
PIC18F8X2X
AD<15:8>
ALE
373
A<20:1>
373
OE
WRH
A<19:16>
WRL
BA0
JEDEC Word
A<x:1>
D<15:0>
A<20:1>
CE
D<15:0>
I/O
OE
WR
(1)
A0
BYTE/WORD
Flash Memory
JEDEC Word
A<x:1>
D<15:0>
CE
D<15:0>
OE
WR
(1)
LB
UB
SRAM Memory
LB
UB
138
(2)
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
2: Demultiplexing is only required when multiple memory devices are accessed.