Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 388  2003-2013 Microchip Technology Inc.
K
Key Features
Easy Migration .............................................................. 7
Expanded Memory........................................................7
External Memory Interface............................................7
Other Special Features .................................................7
L
LFSR.................................................................................299
Low-Voltage Detect...........................................................253
Characteristics ..........................................................333
Converter Characteristics .........................................333
Effects of a Reset...................................................... 257
Operation ..................................................................256
Current Consumption........................................257
During Sleep .....................................................257
Reference Voltage Set Point.............................257
Typical Application....................................................253
Low-Voltage ICSP Programming ......................................274
LVD. See Low-Voltage Detect.
M
Master SSP (MSSP) Module Overview............................. 173
Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP
Memory
Mode Memory Access ................................................40
Memory Maps for PIC18F6X2X/8X2X
Program Memory Modes ............................................41
Memory Organization
Data Memory .............................................................. 47
Program Memory ........................................................39
Modes .................................................................39
Memory Programming Requirements ...............................334
Microcontroller Mode...........................................................71
Microprocessor Mode..........................................................71
Microprocessor with Boot Block Mode ................................71
Migration from High-End to
Enhanced Devices ....................................................379
Migration from Mid-Range to
Enhanced Devices ....................................................378
MOVF................................................................................299
MOVFF.............................................................................. 300
MOVLB..............................................................................300
MOVLW.............................................................................301
MOVWF ............................................................................301
MPLAB ASM30 Assembler, Linker, Librarian ...................318
MPLAB ICD 2 In-Circuit Debugger....................................319
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ....................................319
MPLAB ICE 4000 High-Performance
Universal In-Circuit Emulator ....................................319
MPLAB Integrated Development
Environment Software...............................................317
MPLAB PM3 Device Programmer.....................................319
MPLINK Object Linker/MPLIB Object Librarian ................318
MSSP................................................................................173
ACK
Pulse.........................................................186, 187
Clock Stretching........................................................ 192
10-Bit Slave Receive Mode (SEN = 1)..............192
10-Bit Slave Transmit Mode..............................192
7-Bit Slave Receive Mode (SEN = 1)................ 192
7-Bit Slave Transmit Mode................................192
Clock Synchronization and the
CKP bit (SEN = 1).............................................193
Control Registers (general)....................................... 173
Enabling SPI I/O ....................................................... 177
I
2
C Mode .................................................................. 182
Acknowledge Sequence Timing ....................... 206
Baud Rate Generator ....................................... 199
Bus Collision
During a Repeated
Start Condition.................................. 210
Bus Collision During a Start Condition ............. 208
Bus Collision During a Stop Condition.............. 211
Clock Arbitration ............................................... 200
Effect of a Reset............................................... 207
I
2
C Clock Rate w/BRG ..................................... 199
Master Mode..................................................... 197
Reception ................................................. 203
Repeated Start Condition Timing ............. 202
Start Condition Timing.............................. 201
Transmission ............................................ 203
Multi-Master Communication, Bus
Collision and Arbitration............................ 207
Multi-Master Mode............................................ 207
Registers .......................................................... 182
Sleep Operation................................................ 207
Stop Condition Timing ...................................... 206
Module Operation ..................................................... 186
Operation.................................................................. 176
Slave Mode............................................................... 186
Addressing........................................................ 186
Reception ......................................................... 187
Transmission .................................................... 187
SPI Master Mode...................................................... 178
SPI Mode.................................................................. 173
SPI Slave Mode........................................................ 179
SSPBUF ................................................................... 178
SSPSR ..................................................................... 178
TMR2 Output for Clock Shift............................. 141, 142
TMR4 Output for Clock Shift..................................... 148
Typical Connection ................................................... 177
MSSP Module
SPI Master/Slave Connection................................... 177
MULLW............................................................................. 302
MULWF............................................................................. 302
N
NEGF................................................................................ 303
NOP.................................................................................. 303
O
Oscillator Configuration ...................................................... 21
EC............................................................................... 21
ECIO........................................................................... 21
ECIO+PLL .................................................................. 21
ECIO+SPLL................................................................ 21
HS............................................................................... 21
HS+PLL ...................................................................... 21
HS+SPLL.................................................................... 21
LP ............................................................................... 21
RC .............................................................................. 21
RCIO........................................................................... 21
XT ............................................................................... 21
Oscillator Selection........................................................... 259
Oscillator, Timer1.............................................. 135, 137, 145
Oscillator, Timer3.............................................................. 143
Oscillator, WDT................................................................. 267