Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 38  2003-2013 Microchip Technology Inc.
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR)
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED
(MCLR
TIED TO VDD VIA 1 kRESISTOR)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
T
PLL  2 ms max. First three stages of the PWRT timer.