Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 356  2003-2013 Microchip Technology Inc.
FIGURE 27-22: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 27-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 27-23: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 27-24: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX1/CK1
RC7/RX1/DT1
pin
pin
Note: Refer to Figure 27-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (Master and Slave)
Clock High to Data Out Valid PIC18F6525/6621/
8525/8621
—40ns
PIC18LF6X2X/8X2X — 100 ns
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode)
PIC18F6525/6621/
8525/8621
—20ns
PIC18LF6X2X/8X2X — 50 ns
122 Tdtrf Data Out Rise Time and Fall Time PIC18F6525/6621/
8525/8621
—20ns
PIC18LF6X2X/8X2X — 50 ns
125
126
RC6/TX1/CK1
RC7/RX1/DT1
pin
pin
Note: Refer to Figure 27-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (Master and Slave)
Data Hold before CKx  (DTx hold time) 10 — ns
126 TckL2dtl Data Hold after CKx  (DTx hold time) 15 — ns