Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 346  2003-2013 Microchip Technology Inc.
TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8525/8621)
FIGURE 27-14: EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
TABLE 27-15: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data In Valid before WR
 or CS 
(setup time)
20
25
—
—
ns
ns Extended Temp. range
63 TwrH2dtI WR
 or CS  to Data–in
Invalid (hold time)
PIC18F6525/6621/
8525/8621
20 — ns
PIC18LF6X2X/8X2X 35 — ns
64 TrdL2dtV RD  and CS  to Data–out Valid —
—
80
90
ns
ns Extended Temp. range
65 TrdH2dtI RD
 or CS  to Data–out Invalid 10 30 ns
66 TibfINH Inhibit of the IBF Flag bit being cleared from
WR
 or CS 
—3 T
CY
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In
LSb In
bit 6 - - - -1
Note: Refer to Figure 27-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL
SS
 to SCK  or SCK  Input TCY —ns
71 TscH SCK Input High Time
(Slave mode)
Continuous 1.25 T
CY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK Input Low Time
(Slave mode)
Continuous 1.25 T
CY + 30 — ns
72A Single Byte 40 — ns (Note 1)
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.