Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 34  2003-2013 Microchip Technology Inc.
ADCON0 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu
ADCON1 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu
ADCON2 Feature1 Feature2 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
CCPR2H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON Feature1 Feature2 --00 0000 --00 0000 --uu uuuu
CCPR3H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR3L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
CCP3CON Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
ECCP1AS Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
CVRCON Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
CMCON Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
TMR3H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON Feature1 Feature2 0000 0000 uuuu uuuu uuuu uuuu
PSPCON
(8)
Feature1 Feature2 0000 ---- 0000 ---- uuuu ----
SPBRG1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
RCREG1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
TXREG1 Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
TXSTA1 Feature1 Feature2 0000 0010 0000 0010 uuuu uuuu
RCSTA1 Feature1 Feature2 0000 000x 0000 000x uuuu uuuu
EEADRH Feature1 Feature2 ---- --00 ---- --00 ---- --uu
EEADR Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
EEDATA Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu
EECON2 Feature1 Feature2 ---- ---- ---- ---- ---- ----
EECON1 Feature1 Feature2 xx-0 x000 uu-0 u000 uu-u u000
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR
function is disabled, PORTG<5> is a read-only bit.
8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.