Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 339
PIC18F6525/6621/8525/8621
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
FIGURE 27-6: CLKO AND I/O TIMING
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
Param. No. Sym Characteristic Min Typ† Max Units Conditions
FOSC Oscillator Frequency Range 4 — 10 MHz HS mode
F
SYS On-Chip VCO System Frequency 16 — 40 MHz HS mode
t
rc
PLL Start-up Time (Lock Time) — — 2 ms

CLK CLKO Stability (Jitter) -2 — +2 %
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1  to CLKO  — 75 200 ns (Note 1)
11 TosH2ckH OSC1  to CLKO  — 75 200 ns (Note 1)
12 TckR CLKO Rise Time — 35 100 ns (Note 1)
13 TckF CLKO Fall Time — 35 100 ns (Note 1)
14 TckL2ioV CLKO  to Port Out Valid — — 0.5 T
CY + 20 ns (Note 1)
15 TioV2ckH Port In Valid before CLKO  0.25 T
CY + 25 — — ns (Note 1)
16 TckH2ioI Port In Hold after CLKO  0——ns(Note 1)
17 TosH2ioV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns
18 TosH2ioI OSC1  (Q2 cycle) to Port
Input Invalid (I/O in hold time)
PIC18F6525/6621/
8525/8621
100 — — ns
18A PIC18LF6X2X/8X2X 200 — — ns
19 TioV2osH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns
20 TioR Port Output Rise Time PIC18F6525/6621/
8525/8621
—1025ns
20A PIC18LF6X2X/8X2X — — 60 ns
21 TioF Port Output Fall Time PIC18F6525/6621/
8525/8621
—1025ns
21A PIC18LF6X2X/8X2X — — 60 ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T
OSC.
Note: Refer to Figure 27-4 for load conditions.
OSC1
CLKO
I/O pin
(input)
I/O pin
(output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value