Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 270  2003-2013 Microchip Technology Inc.
FIGURE 24-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT
(1,2)
24.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block is
further divided into a boot block of 2048 bytes and a
second block (Block 0) of 14 Kbytes.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
FIGURE 24-3: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6525/6621/8525/8621
DEVICES
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO
(4)
INT pin
INTF Flag
(INTCON<1>)
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC + 2 PC + 4
Inst(PC) = Sleep
Inst(PC – 1)
Inst(PC + 2)
Sleep
Processor in
Sleep
Interrupt Latency
(3)
Inst(PC + 4)
Inst(PC + 2)
Inst(0008h)
Inst(000Ah)
Inst(0008h)
Dummy Cycle
PC + 4 0008h 000Ah
Dummy Cycle
T
OST
(2)
PC + 4
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: T
OST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
4: CLKO is not available in these oscillator modes but shown here for timing reference.
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
48 Kbytes
(PIC18FX525)
64 Kbytes
(PIC18FX621)
Address
Range
Boot Block Boot Block
000000h
0007FFh
CPB, WRTB, EBTRB
Block 0 Block 0
000800h
003FFFh
CP0, WRT0, EBTR0
Block 1 Block 1
004000h
007FFFh
CP1, WRT1, EBTR1
Block 2 Block 2
008000h
00BFFFh
CP2, WRT2, EBTR2
Unimplemented, read ‘0’ Block 3
00C000h
00FFFFh
CP3, WRT3, EBTR3