Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 26  2003-2013 Microchip Technology Inc.
2.6.2 OSCILLATOR TRANSITIONS
PIC18F6525/6621/8525/8621 devices contain circuitry
to prevent “glitches” when switching between oscillator
sources. Essentially, the circuitry waits for eight rising
edges of the clock source that the processor is switch-
ing to. This ensures that the new clock source is stable
and that its pulse width will not be less than the shortest
pulse width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (T
OST) has occurred. A
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3Q2Q1Q4Q3Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program
PC + 2PC
Note: T
DLY is the delay from SCS high to first count of transition circuit.
Q1
T1OSI
Q4 Q1
Q1
TSCS
Clock
Counter
System
Q2 Q3 Q4 Q1
TDLY
TT1P
TOSC
21 34 5678
PC + 4
Q3
Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program
PC PC + 2
Note: T
OST = 1024 TOSC (drawing not to scale).
T1OSI
System Clock
TOST
Q1
PC + 6
TT1P
TOSC
TSCS
12345678
Counter