Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 212  2003-2013 Microchip Technology Inc.
TABLE 18-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
PSPIF
(1)
ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
(1)
ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
(1)
ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TRISF TRISF7
TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPADD MSSP Address Register in I
2
C Slave mode. MSSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 0000 0000
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I
2
C™ mode.
Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.