Datasheet

PIC18F6525/6621/8525/8621
DS39612C-page 16  2003-2013 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
RE0
AD8
(3)
RD
P2D
24
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 8.
Read control for Parallel Slave Port.
ECCP2 output P2D.
RE1/AD9/WR
/P2C
RE1
AD9
(3)
WR
P2C
13
I/O
I/O
I
O
ST
TTL
TTL
ST
Digital I/O.
External memory address/data 9.
Write control for Parallel Slave Port.
ECCP2 output P2C.
RE2/AD10/CS/P2B
RE2
AD10
(3)
CS
P2B
64 78
I/O
I/O
I
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
ECCP2 output P2B.
RE3/AD11/P3C
RE3
AD11
(3)
P3C
(4)
63 77
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 11.
ECCP3 output P3C.
RE4/AD12/P3B
RE4
AD12
(3)
P3B
(4)
62 76
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 12.
ECCP3 output P3B.
RE5/AD13/P1C
RE5
AD13
(3)
P1C
(4)
61 75
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 13.
ECCP1 output P1C.
RE6/AD14/P1B
RE6
AD14
(3)
P1B
(4)
60 74
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 14.
ECCP1 output P1B.
RE7/AD15/ECCP2/P2A
RE7
AD15
(3)
ECCP2
(5)
P2A
(5)
59 73
I/O
I/O
I/O
O
ST
TTL
ST
—
Digital I/O.
External memory address/data 15.
Enhanced Capture 2 input, Compare 2
output, PWM 2 output.
ECCP2 output P2A.
TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PIC18F6X2X PIC18F8X2X
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AV
DD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP™ modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR
and is only available when the MCLR Resets are disabled.