Datasheet

 2003-2013 Microchip Technology Inc. DS39612C-page 121
PIC18F6525/6621/8525/8621
FIGURE 10-17: MCLR/VPP/RG5 PIN BLOCK DIAGRAM
TABLE 10-13: PORTG FUNCTIONS
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
MCLR/VPP/RG5
Data Bus
RD PORTA
RD LATA
Schmitt
Trigger
MCLRE
RD TRISA
QD
EN
Latch
Filter
Low-Level
MCLR
Detect
High-Voltage Detect
Internal MCLR
HV
Name Bit# Buffer Type Function
RG0/ECCP3/P3A bit 0 ST Input/output port pin, Enhanced Capture 3 input/Compare 3 output/
PWM 3 output or Enhanced PWM 3 output P3A.
RG1/TX2/CK2 bit 1 ST Input/output port pin, addressable USART2 asynchronous transmit or
addressable USART2 synchronous clock.
RG2/RX2/DT2 bit 2 ST Input/output port pin, addressable USART2 asynchronous receive or
addressable USART2 synchronous data.
RG3/CCP4/P3D bit 3 ST Input/output port pin, Capture 4 input/Compare 4 output/PWM 4 output
or Enhanced PWM 3 output P3D.
RG4/CCP5/P1D bit 4 ST Input/output port pin, Capture 5 input/Compare 5 output/PWM 5 output
or Enhanced PWM 1 output P1D.
MCLR
/VPP/RG5 bit 5 ST Master Clear input or programming voltage input (if MCLR is enabled).
Input only port pin or programming voltage input (if MCLR
is
disabled).
Legend: ST = Schmitt Trigger input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTG
— —RG5
(1)
Read PORTG pins/Write PORTG Data Latch --xx xxxx --uu uuuu
LATG
— — — LATG Data Output Register ---x xxxx ---u uuuu
TRISG
— — — Data Direction Control Register for PORTG ---1 1111 ---1 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’
Note 1: RG5 is available as an input only when MCLR is disabled.