PIC18F6525/6621/8525/8621 64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D High Performance RISC CPU: • • • • • • • • External Memory Interface (PIC18F8525/8621 Devices Only): Linear program memory addressing to 64 Kbytes Linear data memory addressing to 4 Kbytes 1 Kbyte of data EEPROM Up to 10 MIPs operation: - DC – 40 MHz osc./clock input - 4 MHz – 10 MHz osc.
PIC18F6525/6621/8525/8621 Pin Diagrams RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RD3/PSP3 RD2/PSP2 RD1/PSP1 VSS VDD RE7/ECCP2(1)/P2A(1) RD0/PSP0 RE6/P1B RE5/P1C RE4/P3B RE3/P3C RE2/CS/P2B 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR/P2C RE0/RD/P2D 1 48 47 46 45 RF4/AN9 2 3 4 5 6 7 8 9 10 11 12 13 14 RF3/AN8 RF2/AN7/C1OUT 15 16 RG0/ECCP3/P3A RG1/TX2/CK2 RG2/RX2/DT2 RG3/CCP4/P3D MCLR/VPP/RG5(2) RG4/CCP5/P1D VSS VDD RF7/SS RF6/AN11 RF5/AN10/CVREF 44 43 42 41 40 PIC18
PIC18F6525/6621/8525/8621 Pin Diagrams (Cont.
PIC18F6525/6621/8525/8621 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 21 3.0 Reset ...........................................................................
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PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 6 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • • • • PIC18F6525 PIC18F6621 PIC18F8525 PIC18F8621 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance Enhanced Flash program memory.
PIC18F6525/6621/8525/8621 1.2 Details on Individual Family Members The PIC18F6525/6621/8525/8621 devices are available in 64-pin (PIC18F6525/6621) and 80-pin (PIC18F8525/8621) packages. They are differentiated from each other in four ways: 1. 2. Flash program memory (48 Kbytes for PIC18F6525/8525 devices; 64 Kbytes for PIC18F6621/8621 devices). A/D channels (12 for PIC18F6525/6621 devices; 16 for PIC18F8525/8621 devices). TABLE 1-1: 3.
PIC18F6525/6621/8525/8621 FIGURE 1-1: PIC18F6525/6621 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/LVDIN OSC2/CLKO/RA6 Data Latch Data RAM (3.
PIC18F6525/6621/8525/8621 FIGURE 1-2: PIC18F8525/8621 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer<21> Data RAM (3.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR/VPP/RG5(9) PIC18F6X2X PIC18F8X2X 7 9 Pin Type Buffer Type MCLR I ST VPP RG5 P I — ST I CMOS/ST I CMOS O — CLKO O — RA6 I/O TTL OSC1/CLKI OSC1 39 49 CLKI OSC2/CLKO/RA6 OSC2 40 50 Description Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 28 30 RA6 27 TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(2) 29 36 33 34 35 RC5/SDO RC5 SDO 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O I I/O ST CMOS ST O — I/O I/O ST ST O — I/O I/O ST ST I/O ST I/O I I/O ST ST ST Digital I/O.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTD is a bidirectional I/O port. These pins have TTL input buffers when external memory is enabled.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTE is a bidirectional I/O port.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 18 RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF1 AN8 15 RF4/AN9 RF1 AN9 14 RF5/AN10/CVREF RF1 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS RF7 SS 11 24 I/O I ST Analog Digital I/O. Analog input 5. I/O I O ST Analog ST Digital I/O.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 3 5 P3A RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2 RG2 RX2 DT2 5 RG3/CCP4/P3D RG3 CCP4 6 8 7 Digital I/O. Enhanced Capture 3 input, Compare 3 output, PWM 3 output. ECCP3 output P3A. O — I/O O I/O ST — ST Digital I/O. USART2 asynchronous transmit.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTH is a bidirectional I/O port(6). RH0/A16 RH0 A16 — RH1/A17 RH1 A17 — RH2/A18 RH2 A18 — RH3/A19 RH3 A19 — RH4/AN12/P3C RH4 AN12 P3C(7) — RH5/AN13/P3B RH5 AN13 P3B(7) — RH6/AN14/P1C RH6 AN14 P1C(7) — RH7/AN15/P1B RH7 AN15 P1B(7) — 79 I/O O ST TTL Digital I/O. External memory address 16.
PIC18F6525/6621/8525/8621 TABLE 1-2: PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X2X PIC18F8X2X Pin Type Buffer Type Description PORTJ is a bidirectional I/O port(6). RJ0/ALE RJ0 ALE — RJ1/OE RJ1 OE — RJ2/WRL RJ2 WRL — RJ3/WRH RJ3 WRH — RJ4/BA0 RJ4 BA0 — RJ5/CE RJ5 CE — RJ6/LB RJ6 LB — RJ7/UB RJ7 UB — 62 I/O O ST TTL Digital I/O. External memory address latch enable. I/O O ST TTL Digital I/O. External memory output enable.
PIC18F6525/6621/8525/8621 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F6525/6621/8525/8621 devices can be operated in twelve different oscillator modes. The user can program four configuration bits (FOSC3, FOSC2, FOSC1 and FOSC0) to select one of these eight modes: 1. 2. 3. 4. 5. 6. LP XT HS RC EC ECIO Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator External Resistor/Capacitor External Clock External Clock with I/O pin enabled 7.
PIC18F6525/6621/8525/8621 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq C1 C2 LP 32.0 kHz 33 pF 33 pF 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF XT HS 4.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.0 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes following this table. Crystals Used 32 kHz 4 MHz 200 kHz 8 MHz 1 MHz 20 MHz 2.
PIC18F6525/6621/8525/8621 2.4 External Clock Input 2.5 The EC, ECIO, EC+PLL and EC+SPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is a maximum 1.5 s start-up required after a Power-on Reset or wake-up from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin.
PIC18F6525/6621/8525/8621 2.6 Oscillator Switching Feature The PIC18F6525/6621/8525/8621 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18F6525/6621/ 8525/8621 devices, this alternate clock source is the Timer1 oscillator.
PIC18F6525/6621/8525/8621 2.6.1 SYSTEM CLOCK SWITCH BIT Note: The system clock source switching is performed under software control. The system clock switch bits, SCS1:SCS0 (OSCCON<1:0>), control the clock switching. When the SCS0 bit is ‘0’, the system clock source comes from the main oscillator that is selected by the FOSC configuration bits in the CONFIG1H Configuration register. When the SCS0 bit is set, the system clock source will come from the Timer1 oscillator.
PIC18F6525/6621/8525/8621 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS0 bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles.
PIC18F6525/6621/8525/8621 If the main oscillator is configured for HS mode with PLL active, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL timeout is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS+PLL mode, is shown in Figure 2-10.
PIC18F6525/6621/8525/8621 If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure 2-12.
PIC18F6525/6621/8525/8621 3.0 RESET The PIC18F6525/6621/8525/8621 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation.
PIC18F6525/6621/8525/8621 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, tie the MCLR pin through a 1 k to 10 k resistor to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e.
PIC18F6525/6621/8525/8621 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Oscillator Configuration Wake-up from Sleep or Oscillator Switch Brown-out PWRTE = 0 PWRTE = 1 HS with PLL enabled(1) 72 ms + 1024 TOSC + 2 ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC + 2 ms HS, XT, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms 1.5 s EC External RC Note 1: 2: 3: 72 ms 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC — 1024 TOSC 72 ms (2) 1.
PIC18F6525/6621/8525/8621 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU Feature1 Feature2 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu(3) TOSL Feature1 Feature2 0000 0000 0000 0000 uuuu uuuu(3) STKPTR Feature1 Feature2 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU Feature1 Feature2 ---0 0
PIC18F6525/6621/8525/8621 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1L Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu BSR Feature1 Feature2 ---- 0000 ---- 0000 ---- uuuu INDF2 Feature1 Feature2 N/A N/A N/A POSTINC2 Feature1 Feature2 N/A N/A N/A POSTDEC2 Feature1 Feature2 N/A N/A N/A PREINC2 Feature1 Fea
PIC18F6525/6621/8525/8621 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADCON0 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu ADCON1 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu ADCON2 Feature1 Feature2 0-00 0000 0-00 0000 u-uu uuuu CCPR1H Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L Feature1 Feature2
PIC18F6525/6621/8525/8621 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR3 Feature1 Feature2 --11 1111 --11 1111 --uu uuuu PIR3 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu PIE3 Feature1 Feature2 --00 0000 --00 0000 --uu uuuu IPR2 Feature1 Feature2 -1-1 1111 -1-1 1111 -u-u uuuu PIR2 Feature1 Feature2 -0-0 0000
PIC18F6525/6621/8525/8621 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt PORTG(7) Feature1 Feature2 --xx xxxx --uu uuuu --uu uuuu PORTF Feature1 Feature2 x000 0000 u000 0000 uuuu uuuu PORTE Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu PORTD Feature1 Feature2 xxxx xxxx uuuu uuuu uuuu uuuu PORTC Feature1 Feature2 xx
PIC18F6525/6621/8525/8621 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 3-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2003-2013 Micro
PIC18F6525/6621/8525/8621 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD VIA 1 kRESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. DS39612C-page 38 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 4.0 MEMORY ORGANIZATION There are three memory blocks in PIC18F6525/6621/ 8525/8621 devices. They are: • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses which allow for concurrent access of these blocks. Additional detailed information for Flash program memory and data EEPROM is provided in Section 5.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively.
PIC18F6525/6621/8525/8621 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FX525 FIGURE 4-2: PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FX621 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 Stack Level 31 000000h Reset Vector Reset Vector 000000h High Priority Interrupt Vector 000008h High Priority Interrupt Vector 000008h Low Priority Interrupt Vector 000018h Low Priority Interrupt Vec
PIC18F6525/6621/8525/8621 REGISTER 4-1: CONFIG3L: CONFIGURATION REGISTER 3 LOW R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable, device will not wait 0 = Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Data Memory Mode Select bits 11 = Microcontroller mode 10 = Microprocessor mode(1) 01 = Microcont
PIC18F6525/6621/8525/8621 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
PIC18F6525/6621/8525/8621 REGISTER 4-2: STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SP4 SP3 SP2 SP1 SP0 STKFUL(1) STKUNF(1) bit 7 bit 0 bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and
PIC18F6525/6621/8525/8621 4.3 Fast Register Stack 4.4 A “fast interrupt return” option is available for interrupts. A fast register stack is provided for the STATUS, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers if the FAST RETURN instruction is used to return from the interrupt.
PIC18F6525/6621/8525/8621 4.6 Instruction Flow/Pipelining A fetch cycle begins with the Program Counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F6525/6621/8525/8621 4.7.1 TWO-WORD INSTRUCTIONS The PIC18F6525/6621/8525/8621 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed.
PIC18F6525/6621/8525/8621 4.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Look-up table data may be stored 2 bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time.
PIC18F6525/6621/8525/8621 FIGURE 4-7: DATA MEMORY MAP FOR PIC18F6525/6621/8525/8621 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 Data Memory Map 00h Access RAM FFh 00h GPRs Bank 0 GPRs Bank 1 FFh 00h Bank 2 1FFh 200h GPRs 2FFh 300h FFh 00h Bank 3 GPRs FFh = 0100 000h 05Fh 060h 0FFh 100h Bank 4 3FFh 400h GPRs Access Bank 4FFh 500h Bank 5 to Bank 13 = 1110 = 1111 00h 5Fh Access RAM high 60h (SFRs) FFh Access RAM low GPRs DFFh E00h 00h Bank 14 GPRs FFh 00h Unused FFh SFRs Bank 1
PIC18F6525/6621/8525/8621 TABLE 4-2: Address SPECIAL FUNCTION REGISTER MAP Name Address Name (3) Address Name Address Name FFFh TOSU FDFh FBFh CCPR1H F9Fh IPR1 FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1 FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch MEMCON(2) FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —(1) FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(2) FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRI
PIC18F6525/6621/8525/8621 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name F7Fh SPBRGH1 Address F5Fh Name (1) — (1) Address F3Fh Name Address Name (1) F1Fh —(1) (1) — F7Eh BAUDCON1 F5Eh — F3Eh — F1Eh —(1) F7Dh SPBRGH2 F5Dh —(1) F3Dh —(1) F1Dh —(1) F7Ch F5Ch —(1) F3Ch —(1) F1Ch —(1) F7Bh BAUDCON2 —(1) F5Bh — (1) F3Bh — (1) F1Bh —(1) F7Ah —(1) F5Ah —(1) F3Ah —(1) F1Ah —(1) F39h —(1) F19h —(1) F79h ECCP1DEL F59h —(1) F78h TMR
PIC18F6525/6621/8525/8621 TABLE 4-3: File Name REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 32, 42 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 32, 42 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 32, 42 TOSU STKPTR PCLATU Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR STKFUL STKUNF — Return Stack Pointer 00-0 0000 32, 43 — — — Holding Register for PC<20:16> ---0 0000 32, 44 PCLATH Holding Regist
PIC18F6525/6621/8525/8621 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 56 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by value in WREG N/A 56 — FSR2H FSR2L — — — Indirect Data Memory Address
PIC18F6525/6621/8525/8621 TABLE 4-3: File Name CMCON REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 Value on POR, BOR Details on page: 0000 0000 34, 243 TMR3H Timer3 Register High Byte xxxx xxxx 34, 145 TMR3L Timer3 Register Low Byte xxxx xxxx 34, 145 T3CON PSPCON(5) RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 34, 145 IBF OBF IBOV PSPMODE — — — — 0000 ---- 34, 129
PIC18F6525/6621/8525/8621 TABLE 4-3: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: PORTJ(3) Read PORTJ pins, Write PORTJ Data Latch xxxx xxxx 35, 127 PORTH(3) Read PORTH pins, Write PORTH Data Latch 0000 xxxx 35, 124 --xx xxxx 36, 121 PORTG — — RG5 (4) Read PORTG pins, Write PORTG Data Latch PORTF Read PORTF pins, Write PORTF Data Latch x000 0000 36, 119 PORTE Read PORTE pins, Write PORTE Data La
PIC18F6525/6621/8525/8621 4.10 Access Bank 4.11 The Access Bank is an architectural enhancement, which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank.
PIC18F6525/6621/8525/8621 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-9 shows the operation of indirect addressing.
PIC18F6525/6621/8525/8621 FIGURE 4-9: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> Instruction Fetched Opcode FIGURE 4-10: 4 12 12 8 File FSR INDIRECT ADDRESSING Indirect Addressing 11 FSR Register 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-2. 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 4.13 STATUS Register The STATUS register, shown in Register 4-3, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed.
PIC18F6525/6621/8525/8621 4.14 RCON Register Note: The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 4-4: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 60 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 5.0 FLASH PROGRAM MEMORY 5.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable, during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time.
PIC18F6525/6621/8525/8621 FIGURE 5-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 5.2 Table pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 5.5 “Writing to Flash Program Memory”.
PIC18F6525/6621/8525/8621 REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash R
PIC18F6525/6621/8525/8621 5.2.2 TABLAT – TABLE LATCH REGISTER 5.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F6525/6621/8525/8621 5.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 5-4: TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words.
PIC18F6525/6621/8525/8621 5.4 5.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18F6525/6621/8525/8621 5.5 Writing to Flash Program Memory The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation.
PIC18F6525/6621/8525/8621 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; p
PIC18F6525/6621/8525/8621 EXAMPLE 5-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF EECON1, EEPGD BCF EECON1, CFGS BSF EECON1, WREN BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE DECFSZ COUNTER_HI BRA PROGRAM_LOOP BCF EECON1, WREN Required Sequence 5.5.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 70 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 6.0 EXTERNAL MEMORY INTERFACE 6.1 Note: The external memory interface is not implemented on PIC18F6525/6621 (64-pin) devices. The external memory interface is a feature of the PIC18F8525/8621 devices that allows the controller to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. The physical implementation of the interface uses 27 pins.
PIC18F6525/6621/8525/8621 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports.
PIC18F6525/6621/8525/8621 6.2 16-Bit Mode The external memory interface implemented in PIC18F8525/8621 devices operates only in 16-bit mode. The mode selection is not software configurable but is programmed via the configuration bits. The WM1:WM0 bits in the MEMCON register determine three types of connections in 16-bit mode.
PIC18F6525/6621/8525/8621 6.2.2 16-BIT WORD WRITE MODE Figure 6-2 shows an example of 16-bit Word Write mode for PIC18F8525/8621 devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of wordwide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F6525/6621/8525/8621 6.2.3 16-BIT BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8525/8621 devices. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F6525/6621/8525/8621 6.2.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 6-4 through Figure 6-6.
PIC18F6525/6621/8525/8621 FIGURE 6-6: EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE) Q1 Q2 Q4 Q1 Q2 3AAAh Q3 Q4 Q1 00h 00h A<19:16> AD<15:0> Q3 0003h 3AABh 0E55h CE ALE OE Memory Cycle Instruction Execution Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h INST(PC – 2) SLEEP 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 78 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are five SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • • EECON1 EECON2 EEDATA EEADRH EEADR The EEPROM data memory allows byte read and write.
PIC18F6525/6621/8525/8621 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration or Calibration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 F
PIC18F6525/6621/8525/8621 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADRH:EEADR register pair, clear the EEPGD control bit (EECON1<7>), clear the CFGS EXAMPLE 7-1: MOVLW MOVWF MOVLW MOVWF BCF BCF BSF MOVF 7.
PIC18F6525/6621/8525/8621 7.5 Write Verify 7.7 Operation During Code-Protect Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Data EEPROM memory has its own code-protect mechanism. External read and write operations are disabled if either of these mechanisms are enabled. Refer to Section 24.
PIC18F6525/6621/8525/8621 TABLE 7-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 INTCON GIE/GIEH EEADRH — Bit 6 Bit 5 PEIE/GIEL TMR0IE — — Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — — — Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets INT0IF RBIF 0000 000x 0000 000u EE Addr Register High ---- --00 ---- --00 EEADR Data EEPROM Address Register 0000 0000 0000 0000 EEDATA Data EEPROM Data Register 0000 0000 0000 0000 EECON2 Data EEPROM Control Register 2 (no
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 84 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction 8.2 Operation Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. An 8 x 8 hardware multiplier is included in the ALU of the PIC18F6525/6621/8525/8621 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18F6525/6621/8525/8621 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
PIC18F6525/6621/8525/8621 9.0 INTERRUPTS The PIC18F6525/6621/8525/8621 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h, while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation.
PIC18F6525/6621/8525/8621 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Sleep mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit GIEH/GIE TMR1IF TMR1IE TMR1IP IPEN IPEN XXXXIF XXXXIE XXXXIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral I
PIC18F6525/6621/8525/8621 9.1 INTCON Registers Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. The INTCON registers are readable and writable registers which contain various enable, priority and flag bits.
PIC18F6525/6621/8525/8621 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select
PIC18F6525/6621/8525/8621 REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external in
PIC18F6525/6621/8525/8621 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request Flag registers (PIR1, PIR2 and PIR3).
PIC18F6525/6621/8525/8621 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIF: Comparator Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed bit 5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write op
PIC18F6525/6621/8525/8621 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 U-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IF: USART2 Receive Interrupt Flag bit 1 = The USART2 receive buffer, RCREGx, is full (cleared when RCREGx is read) 0 = The USART2 receive buffer is empty bit 4 TX2IF: USART2 Transmit Interrupt Flag bit 1 = The USART2 transmit buffer, TXREGx, is empty (cle
PIC18F6525/6621/8525/8621 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F6525/6621/8525/8621 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enables the write operation interrupt 0 = Disable
PIC18F6525/6621/8525/8621 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IE: USART2 Receive Interrupt Enable bit 1 = Enables the USART2 receive interrupt 0 = Disables the USART2 receive interrupt bit 4 TX2IE: USART2 Transmit Interrupt Enable bit 1 = Enables the USART2 transmit interrupt 0 = Disables the USART2 transmit interrupt
PIC18F6525/6621/8525/8621 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F6525/6621/8525/8621 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit
PIC18F6525/6621/8525/8621 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 RC2IP: USART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX2IP: USART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority
PIC18F6525/6621/8525/8621 9.5 RCON Register The RCON register contains the IPEN bit which is used to enable prioritized interrupts. The functions of the other bits in this register are discussed in more detail in Section 4.14 “RCON Register”.
PIC18F6525/6621/8525/8621 9.6 INT0 Interrupt 9.8 External interrupts on the RB0/INT0/FLT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered; either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18F6525/6621/8525/8621 10.0 I/O PORTS 10.1 Depending on the device selected, there are either seven or nine I/O ports available on PIC18F6525/6621/ 8525/8621 devices. Some of their pins are multiplexed with one or more alternate functions from the other peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F6525/6621/8525/8621 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS FIGURE 10-3: BLOCK DIAGRAM OF RA4/T0CKI PIN RD LATA RD LATA Data Bus D WR LATA or PORTA Data Bus Q WR LATA or PORTA VDD CK Q P WR TRISA N Q I/O pin(1) WR TRISA CK Q CK Q N Data Latch Data Latch D D VSS Analog Input Mode Q TRIS Latch D Q CK Q I/O pin(1) VSS Schmitt Trigger Input Buffer TRIS Latch RD TRISA RD TRISA Q D TTL Input Buffer Q D ENEN EN RD PORTA RD PORTA TMR0 Clock Input To A/D C
PIC18F6525/6621/8525/8621 TABLE 10-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF- bit 2 TTL Input/output, analog input or VREF-. RA3/AN3/VREF+ bit 3 TTL Input/output, analog input or VREF+. RA4/T0CKI bit 4 ST Input/output or external clock input for Timer0. Output is open-drain type. RA5/AN4/LVDIN bit 5 TTL Input/output, analog input or Low-Voltage Detect input.
PIC18F6525/6621/8525/8621 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F6525/6621/8525/8621 FIGURE 10-6: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus WR LATB or WR PORTB I/O pin(1) CK TRIS Latch D WR TRISB Q TTL Input Buffer CK RD TRISB Q D RD PORTB EN INTx Schmitt Trigger Buffer Note 1: 2: FIGURE 10-7: RD Port I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
PIC18F6525/6621/8525/8621 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0/FLT0 bit 0 TTL/ST(1) Input/output pin or external interrupt input 0, ECCP1 PWM Fault input. Internal software programmable weak pull-up. RB1/INT1 bit 1 TTL/ST(1) Input/output pin or external interrupt input 1. Internal software programmable weak pull-up. RB2/INT2 bit 2 TTL/ST(1) Input/output pin or external interrupt input 2. Internal software programmable weak pull-up.
PIC18F6525/6621/8525/8621 10.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode).
PIC18F6525/6621/8525/8621 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T13CKI bit 0 ST Input/output port pin, Timer1 oscillator output or Timer1/Timer3 clock input. RC1/T1OSI/ ECCP2(1)/P2A(1) bit 1 ST Input/output port pin, Timer1 oscillator input, Enhanced Capture 2 input/Compare 2 output/PWM 2 output or Enhanced PWM output P2A. RC2/ECCP1/P1A bit 2 ST Input/output port pin, Enhanced Capture 1 input/Compare 1 output/ PWM 1 output or Enhanced PWM output P1A.
PIC18F6525/6621/8525/8621 10.4 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped.
PIC18F6525/6621/8525/8621 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTD RD LATD Data Bus D WR LATD or PORTD CK Q Port Data I/O pin(1) 0 1 Data Latch D WR TRISD Q CK TRIS Latch TTL Input Buffer RD TRISD System Bus Control Bus Enable Data/TRIS Out Drive Bus Instruction Register Instruction Read Note 1: DS39612C-page 112 I/O pins have protection diodes to VDD and VSS. 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 TABLE 10-7: PORTD FUNCTIONS Name Bit# Buffer Type Function RD0/AD0(2)/PSP0 bit 0 ST/TTL(1) Input/output port pin, address/data bus bit 0 or Parallel Slave Port bit 0. bit 1 ST/TTL (1) Input/output port pin, address/data bus bit 1 or Parallel Slave Port bit 1. (1) Input/output port pin, address/data bus bit 2 or Parallel Slave Port bit 2.
PIC18F6525/6621/8525/8621 10.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F6525/6621/8525/8621 FIGURE 10-11: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out VDD 0 P RD LATE 1 Data Bus WR LATE or WR PORTE D Q CK Q Data Latch WR TRISE D Q CK Q I/O pin(1) N VSS TRIS Override TRIS OVERRIDE TRIS Latch Pin Override Peripheral RE0 Yes External Bus RE1 Yes External Bus RE2 Yes External Bus RE3 Yes External Bus RE4 Yes External Bus RD PORTE RE5 Yes External Bus Peripheral Data In RE6 Yes External Bus Note 1: I
PIC18F6525/6621/8525/8621 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/AD8/RD/P2D bit 0 ST/TTL(1) Input/output port pin, address/data bit 8, read control for Parallel Slave Port or Enhanced PWM 2 output P2D For RD (PSP Control mode): 1 = Not a read operation 0 = Read operation, reads PORTD register (if chip selected) RE1/AD9/WR/P2C bit 1 ST/TTL(1) Input/output port pin, address/data bit 9, write control for Parallel Slave Port or Enhanced PWM 2 output P2C For WR (PSP Control m
PIC18F6525/6621/8525/8621 10.6 EXAMPLE 10-6: PORTF, LATF and TRISF Registers CLRF PORTF is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F6525/6621/8525/8621 FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM D WR LATF or WR PORTF D WR LATF or WR PORTF CK Q VDD CK Data Bus Q P D VSS Analog Input Mode Q TRIS Latch Q Schmitt Trigger Input Buffer I/O pin WR TRISF CK I/O pin D N Q Q Data Latch Data Latch WR TRISF RF7 PIN BLOCK DIAGRAM RD LATF RD LATF Data Bus FIGURE 10-15: CK TRIS Latch TTL Input Buffer RD TRISF RD TRISF ST Input Buffer Q Q D D ENEN EN RD PORTF RD PORTF SS Input To A/D Converter or Compar
PIC18F6525/6621/8525/8621 TABLE 10-11: PORTF FUNCTIONS Name Bit# Buffer Type Function RF0/AN5 bit 0 ST Input/output port pin or analog input. RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or Comparator 2 output. RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or Comparator 1 output. RF3/AN8 bit 3 ST Input/output port pin or analog input/comparator input. RF4/AN9 bit 4 ST Input/output port pin or analog input/comparator input.
PIC18F6525/6621/8525/8621 10.7 PORTG, TRISG and LATG Registers The sixth pin of PORTG (MCLR/VPP/RG5) is a digital input pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). In its default configuration (MCLRE = 1), the pin functions as the device Master Clear input. When selected as a port pin (MCLRE = 0), it functions as an input only pin; as such, it does not have TRISG or LATG bits associated with it.
PIC18F6525/6621/8525/8621 FIGURE 10-17: MCLR/VPP/RG5 PIN BLOCK DIAGRAM MCLRE Data Bus MCLR/VPP/RG5 RD TRISA Schmitt Trigger RD LATA Latch Q D EN RD PORTA High-Voltage Detect HV Internal MCLR Filter Low-Level MCLR Detect TABLE 10-13: PORTG FUNCTIONS Name Bit# Buffer Type Function RG0/ECCP3/P3A bit 0 ST Input/output port pin, Enhanced Capture 3 input/Compare 3 output/ PWM 3 output or Enhanced PWM 3 output P3A.
PIC18F6525/6621/8525/8621 10.8 Note: PORTH, LATH and TRISH Registers PORTH is available only on PIC18F8525/ 8621 devices. FIGURE 10-18: RD LATH PORTH is an 8-bit wide, bidirectional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e.
PIC18F6525/6621/8525/8621 FIGURE 10-20: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTH RD LATH Data Bus WR LATH or PORTH D Q Port I/O pin(1) 0 Data 1 CK Data Latch D WR TRISH Q CK TRIS Latch TTL Input Buffer RD TRISH External Enable System Bus Control Address Out Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type Function bit 0 ST/TTL(1) Input/output port pin or address bit 16 for external memory interface. bit 1 ST/TTL(1) Input/output port pin or address bit 17 for external memory interface. RH2/A18 bit 2 ST/TTL (1) Input/output port pin or address bit 18 for external memory interface. RH3/A19 bit 3 ST/TTL(1) Input/output port pin or address bit 19 for external memory interface.
PIC18F6525/6621/8525/8621 10.9 Note: PORTJ, TRISJ and LATJ Registers PORTJ is available only on PIC18F8525/ 8621 devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin).
PIC18F6525/6621/8525/8621 FIGURE 10-22: RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D ENEN RD PORTJ RD LATJ Data Bus D I/O pin(1) Port Q 0 Data WR LATJ or PORTJ 1 CK Data Latch D WR TRISJ Q CK TRIS Latch RD TRISJ Control Out System Bus Control External Enable Drive System Note 1: I/O pins have diode protection to VDD and VSS.
PIC18F6525/6621/8525/8621 TABLE 10-17: PORTJ FUNCTIONS Name Bit# Buffer Type Function RJ0/ALE bit 0 ST Input/output port pin or address latch enable control for external memory interface. RJ1/OE bit 1 ST Input/output port pin or output enable control for external memory interface. RJ2/WRL bit 2 ST Input/output port pin or write low byte control for external memory interface. RJ3/WRH bit 3 ST Input/output port pin or write high byte control for external memory interface.
PIC18F6525/6621/8525/8621 10.10 Parallel Slave Port PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set. It is asynchronously readable and writable by the external world through RD control input pin, RE0/RD and WR control input pin, RE1/WR. Note: For PIC18F8525/8621 devices, the Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC18F6525/6621/8525/8621 REGISTER 10-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER(1) R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 =
PIC18F6525/6621/8525/8621 FIGURE 10-26: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 PO
PIC18F6525/6621/8525/8621 11.
PIC18F6525/6621/8525/8621 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 1 1 T0CKI pin Programmable Prescaler 0 TMR0 (2 TCY Delay) T0SE 3 Sync with Internal Clocks PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
PIC18F6525/6621/8525/8621 11.1 11.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control, (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 134 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from ECCP module special event trigger Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 oscillator enable bit (T1OSCEN).
PIC18F6525/6621/8525/8621 12.1 Timer1 Operation When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. That is, the TRISC<1:0> value is ignored and the pins are read as ‘0’. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter Timer1 also has an internal “Reset input”. This Reset can be generated by the ECCP1 or ECCP2 special event trigger. This is discussed in detail in Section 12.
PIC18F6525/6621/8525/8621 12.2 Timer1 Oscillator 12.3 Timer1 Interrupt A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator.
PIC18F6525/6621/8525/8621 12.6 Using Timer1 as a Real-Time Clock the routine which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 “Timer1 Oscillator”) gives users the option to include RTC functionality to their applications.
PIC18F6525/6621/8525/8621 TABLE 12-2: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP SSPIP C
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 140 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 MSSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 13-1.
PIC18F6525/6621/8525/8621 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock.
PIC18F6525/6621/8525/8621 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from ECCP module trigger REGISTER 14-1: Register 14-1 shows the Timer3 Control register.
PIC18F6525/6621/8525/8621 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs.
PIC18F6525/6621/8525/8621 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated up to 200 kHz. See Section 12.0 “Timer1 Module” for further details. 14.3 The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 146 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 15.0 TIMER4 MODULE 15.1 The Timer4 module timer has the following features: • • • • • • 8-bit timer (TMR4 register) 8-bit period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 15-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption.
PIC18F6525/6621/8525/8621 15.2 Timer4 Interrupt 15.3 The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCP modules. It is not used as a baud rate clock for the MSSP, as is the Timer2 output.
PIC18F6525/6621/8525/8621 16.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F6525/6621/8525/8621 devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) implement standard Capture and Compare modes, as well as Enhanced PWM modes. These are discussed in Section 17.0 “Enhanced Capture/Compare/PWM (ECCP) Module”.
PIC18F6525/6621/8525/8621 16.1 TABLE 16-1: CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register in turn is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 CCP MODULES AND TIMER RESOURCES The CCP/ECCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected.
PIC18F6525/6621/8525/8621 16.2 16.2.3 Capture Mode In Capture mode, the CCPR4H:CCPR4L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RG3/CCP4/P1D. An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge 16.2.1 CCP PIN CONFIGURATION In Capture mode, the RG3/CCP4/P1D pin should be configured as an input by setting the TRISG<3> bit. Note: 16.2.
PIC18F6525/6621/8525/8621 16.3 16.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP4 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 16.3.
PIC18F6525/6621/8525/8621 TABLE 16-2: Name INTCON RCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 GIE/GIEH PEIE/GIEL Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u Bit 6 IPEN — — RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1I
PIC18F6525/6621/8525/8621 16.4 16.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces up to a 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with the PORTG data latch, the TRISG<3> bit must be cleared to make the CCP4 pin an output. Note: Clearing the CCP4CON register will force the CCP4 PWM output latch to the default low level. This is not the PORTG I/O data latch. Figure 16-4 shows a simplified block diagram of the CCP module in PWM mode.
PIC18F6525/6621/8525/8621 The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 16-3: 16.4.3 The following steps should be taken when configuring the CCP module for PWM operation: 1. F OSC log --------------- F PWM PWM Resolution (max) = -----------------------------bits log 2 2. 3. Note: If the PWM duty cycle value is longer than the PWM period, the CCP4 pin will not be cleared. 4. 5. 6.
PIC18F6525/6621/8525/8621 TABLE 16-4: Name INTCON RCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u BOR 0--1 11qq 0--q qquu IPEN — — RI TO PD POR PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0
PIC18F6525/6621/8525/8621 17.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE Capture and Compare functions of the ECCP module are the same as the standard CCP module. The prototype control register for the Enhanced CCP module is shown in Register 17-1. In addition to the expanded range of modes available through the CCPxCON register, the ECCP modules each have two additional registers associated with Enhanced PWM operation and auto-shutdown features.
PIC18F6525/6621/8525/8621 17.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration.
PIC18F6525/6621/8525/8621 TABLE 17-2: ECCP Mode PIN CONFIGURATIONS FOR ECCP2 CCP2CON Configuration RB3 RC1 RE7 RE2 RE1 RE0 All devices, CCP2MX = 1, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 P2B P2C P2D All devices, CCP2MX = 0, Microcontroller mode: Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OS1 ECCP2 RE2 RE1 RE0 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OS1
PIC18F6525/6621/8525/8621 17.1.3 ECCP MODULES AND TIMER RESOURCES Like the standard CCP modules, the ECCP modules can utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 16.1.1 “CCP Modules and Timer Resources”. 17.
PIC18F6525/6621/8525/8621 FIGURE 17-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCP1M<3:0> 4 P1M1<1:0> 2 CCPR1L ECCP1/P1A ECCP1/P1A TRISx CCPR1H (Slave) P1B R Comparator Output Controller Q P1B TRISx P1C TMR2 (Note 1) P1D Comparator PR2 P1C TRISx S Clear Timer, set ECCP1 pin and latch D.C.
PIC18F6525/6621/8525/8621 17.4.3 PWM OUTPUT CONFIGURATIONS The Single Output mode is the standard PWM mode discussed in Section 17.4 “Enhanced PWM Mode”. The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow.
PIC18F6525/6621/8525/8621 FIGURE 17-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 CCP1CON <7:6> 00 (Single Output) PR2 + 1 Duty Cycle SIGNAL Period P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1C
PIC18F6525/6621/8525/8621 FIGURE 17-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) PIC18F6X2X/8X2X FET Driver + V - P1A Load FET Driver + V - P1B V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F6X2X/8X2X FET Driver FET Driver P1A FET Driver Load FET Driver P1B V- DS39612C-page 164 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 17.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 17-6. FIGURE 17-6: P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches.
PIC18F6525/6621/8525/8621 FIGURE 17-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F6X2X/8X2X FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 17.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F6525/6621/8525/8621 FIGURE 17-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F6525/6621/8525/8621 17.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F6525/6621/8525/8621 REGISTER 17-3: ECCPxAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 bit 7 ECCPxASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6-4 ECCPxAS2:ECCPxAS0: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comp
PIC18F6525/6621/8525/8621 17.4.7.1 Auto-Shutdown and Automatic Restart 17.4.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 17-10), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared.
PIC18F6525/6621/8525/8621 17.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: 1. 2. 3. 4. 5. 6. 7. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 register.
PIC18F6525/6621/8525/8621 TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u IPEN — — RI TO PD POR BOR 0--1 11qq 0--q qquu PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000
PIC18F6525/6621/8525/8621 18.0 18.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18F6525/6621/8525/8621 18.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18F6525/6621/8525/8621 REGISTER 18-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF regis
PIC18F6525/6621/8525/8621 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
PIC18F6525/6621/8525/8621 18.3.3 ENABLING SPI I/O 18.3.4 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18F6525/6621/8525/8621 18.3.5 MASTER MODE The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 18-3, Figure 18-5 and Figure 18-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK.
PIC18F6525/6621/8525/8621 18.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state.
PIC18F6525/6621/8525/8621 FIGURE 18-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF FIGURE 18-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bi
PIC18F6525/6621/8525/8621 18.3.8 SLEEP OPERATION 18.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 18-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 18-1: In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device.
PIC18F6525/6621/8525/8621 18.4 I2C Mode 18.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F6525/6621/8525/8621 REGISTER 18-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Add
PIC18F6525/6621/8525/8621 REGISTER 18-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it i
PIC18F6525/6621/8525/8621 REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was re
PIC18F6525/6621/8525/8621 18.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18F6525/6621/8525/8621 18.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set.
DS39612C-page 188 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
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DS39612C-page 190 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A1 Cleared in
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PIC18F6525/6621/8525/8621 18.4.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 18.4.4.
PIC18F6525/6621/8525/8621 18.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 18-12: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS39612C-page 194 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs
2003-2013 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18F6525/6621/8525/8621 18.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F6525/6621/8525/8621 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F6525/6621/8525/8621 18.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18F6525/6621/8525/8621 18.4.7 BAUD RATE GENERATOR Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 18-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting.
PIC18F6525/6621/8525/8621 18.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 18-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18F6525/6621/8525/8621 18.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC18F6525/6621/8525/8621 18.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<5:0> and begins counting.
PIC18F6525/6621/8525/8621 18.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
DS39612C-page 204 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W Start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Da
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PIC18F6525/6621/8525/8621 18.4.12 ACKNOWLEDGE SEQUENCE TIMING 18.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18F6525/6621/8525/8621 18.4.14 SLEEP OPERATION 18.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 18.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 18.4.
PIC18F6525/6621/8525/8621 18.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 18-26). SCL is sampled low before SDA is asserted low (Figure 18-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 18-28).
PIC18F6525/6621/8525/8621 FIGURE 18-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F6525/6621/8525/8621 18.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 18-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F6525/6621/8525/8621 18.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 18-31).
PIC18F6525/6621/8525/8621 TABLE 18-4: Name REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF(1) ADIF RC1IF PIE1 PSPIE(1) ADIE IPR1 PSPIP(1) ADIP TRISC TRISF Bit 1 Bit 0 TRISF6 Value on all other Resets Bit 2 INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 RC1IP TX1IP SSPIP CCP1IP TMR2IP
PIC18F6525/6621/8525/8621 19.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F6525/6621/8525/8621 REGISTER 19-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC R/W-0 SENDB bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F6525/6621/8525/8621 REGISTER 19-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.
PIC18F6525/6621/8525/8621 REGISTER 19-3: BAUDCONx: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode.
PIC18F6525/6621/8525/8621 19.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18F6525/6621/8525/8621 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — — — 1.221 1.73 255 2.404 Actual Rate (K) % Error 0.3 — — 1.2 — 2.4 2.441 SPBRG value SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — — — 1.73 255 1.202 0.16 129 2.404 SPBRG value FOSC = 8.
PIC18F6525/6621/8525/8621 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1.2 1.200 0.02 2082 1.200 -0.
PIC18F6525/6621/8525/8621 19.1.2 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 19-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. as a 16-bit counter.
PIC18F6525/6621/8525/8621 19.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and flag bit TXxIF is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXxIE. Flag bit TXxIF will be set regardless of the state of enable bit TXxIE and cannot be cleared in software. Flag bit TXxIF is not cleared immediately upon loading the Transmit Buffer register, TXREGx.
PIC18F6525/6621/8525/8621 FIGURE 19-3: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 19-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 1 TCY TXxIF bit (Interrupt Reg.
PIC18F6525/6621/8525/8621 19.2.2 EUSART ASYNCHRONOUS RECEIVER 19.2.3 The receiver block diagram is shown in Figure 19-5. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F6525/6621/8525/8621 FIGURE 19-6: ASYNCHRONOUS RECEPTION Start bit bit 0 RXx (pin) bit 1 bit 7/8 Stop bit Start bit bit 7/8 bit 0 Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx Stop bit RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer register) is read after the third word causing the OERR (overrun) bit to be set.
PIC18F6525/6621/8525/8621 19.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line, while the EUSART is operating in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>).
PIC18F6525/6621/8525/8621 19.2.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift register is loaded with data.
PIC18F6525/6621/8525/8621 19.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCYCLE), the TXREGx is empty and interrupt bit TXxIF is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXxIE. Flag bit TXxIF will be set regardless of the state of enable bit TXxIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F6525/6621/8525/8621 FIGURE 19-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit TABLE 19-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSP
PIC18F6525/6621/8525/8621 19.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F6525/6621/8525/8621 TABLE 19-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE (1) ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RC1IP TX1IP S
PIC18F6525/6621/8525/8621 19.4 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 19.4.
PIC18F6525/6621/8525/8621 19.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCxIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN.
PIC18F6525/6621/8525/8621 20.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: The analog-to-digital (A/D) converter module has 12 inputs for the PIC18F6525/6621 devices and 16 for the PIC18F8525/8621 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time.
PIC18F6525/6621/8525/8621 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits: A/D VREF+ A/D VREF- 00 AVDD AVSS 01 External VREF+ AVSS 10 AVDD External VREF- 11 External VREF+ External VREF- PCFG3 PCFG0 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 PCFG3:PCF
PIC18F6525/6621/8525/8621 REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Se
PIC18F6525/6621/8525/8621 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ pin and RA2/AN2/VREF- pin. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion is aborted. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference), or as a digital I/O.
PIC18F6525/6621/8525/8621 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. 2. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1 “A/D Acquisition Requirements”.
PIC18F6525/6621/8525/8621 20.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F6525/6621/8525/8621 20.2 Selecting and Configuring Acquisition Time 20.3 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable.
PIC18F6525/6621/8525/8621 20.4 Configuring Analog Port Pins The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits.
PIC18F6525/6621/8525/8621 20.6 Use of the ECCP2 Trigger An A/D conversion can be started by the special event trigger of the ECCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/ DONE bit will be set, starting the A/D conversion and the Timer1 (or Timer3) counter will be reset to zero.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 242 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 21.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RF1 through RF6 pins. The onchip Voltage Reference (Section 22.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 21-1: The CMCON register, shown as Register 21-1, controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 21-1.
PIC18F6525/6621/8525/8621 21.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 21-1 shows the eight possible modes. The TRISF register controls the data direction of the comparator pins for each mode.
PIC18F6525/6621/8525/8621 21.2 21.3.2 Comparator Operation INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 21-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F6525/6621/8525/8621 FIGURE 21-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RF1 or RF2 Pin Bus Data Q Read CMCON Set CMIF bit D EN Q From Other Comparator D EN CL Read CMCON Reset 21.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F6525/6621/8525/8621 21.7 Comparator Operation During Sleep 21.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications.
PIC18F6525/6621/8525/8621 TABLE 21-1: Name CMCON REGISTERS ASSOCIATED WITH COMPARATOR MODULE INTCON Bit 3 Bit 2 Bit 1 Bit 0 Value on all other Resets Bit 6 Bit 5 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 0000 0000 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u CVRCON CVREN CVROE Bit 4 Value on POR Bit 7 GIE/ GIEH PEIE/ GIEL PIR2 — CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 -0-0 0000 PIE2
PIC18F6525/6621/8525/8621 22.0 COMPARATOR VOLTAGE REFERENCE MODULE 22.1 The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 22-1. The block diagram is given in Figure 22-1.
PIC18F6525/6621/8525/8621 FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM AVDD VREF+ CVRSS = 0 16 Stages CVRSS = 1 CVREN 8R R R R R CVRR 8R CVRSS = 0 CVRSS = 1 CVREF 16-1 Analog Mux VREFCVR3 (From CVRCON<3:0>) CVR0 Note: R is defined in Section 27.0 “Electrical Characteristics”. 22.2 Voltage Reference Accuracy/Error 22.4 Effects of a Reset The full range of voltage reference cannot be realized due to the construction of the module.
PIC18F6525/6621/8525/8621 FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) CVREF Module RF5 + – CVREF Output Voltage Reference Output Impedance Note 1: TABLE 22-1: Name R is dependent upon the voltage reference configuration bits, CVRCON<3:0> and CVRCON<5>.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 252 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 23.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module.
PIC18F6525/6621/8525/8621 FIGURE 23-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVDL3:LVDL0 LVDCON Register 16 to 1 MUX VDD Internally Generated Reference Voltage LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin, FIGURE 23-3: LVDIF LVDIN (Figure 23-3).
PIC18F6525/6621/8525/8621 23.1 Control Register The Low-Voltage Detect (Register 23-1) controls the Low-Voltage Detect circuitry.
PIC18F6525/6621/8525/8621 23.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3.
PIC18F6525/6621/8525/8621 23.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 258 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 24.0 SPECIAL FEATURES OF THE CPU Sleep mode is designed to offer a very low current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits is used to select various options.
PIC18F6525/6621/8525/8621 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — OSCSEN — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4 Unimplemented: Read
PIC18F6525/6621/8525/8621 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOR PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.0V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.
PIC18F6525/6621/8525/8621 REGISTER 24-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1) R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 WAIT — — — — — PM1 PM0 bit 7 bit 0 bit 7 WAIT: External Bus Data Wait Enable bit 1 = Wait selections unavailable for table reads and table writes 0 = Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) bit 6-2 Unimplemented: Read as ‘0’ bit 1-0 PM1:PM0: Processor Mode Select bits 11 = Microcontrol
PIC18F6525/6621/8525/8621 REGISTER 24-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug.
PIC18F6525/6621/8525/8621 REGISTER 24-8: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) not code-protected 0 = Boot block (000000-0007FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Cle
PIC18F6525/6621/8525/8621 REGISTER 24-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/C-1 R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0007FFh) not write-protected 0 = Boot block (000000-0007FFh) write-protected bit 5 WRTC: Configuration Register Write Protection
PIC18F6525/6621/8525/8621 REGISTER 24-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0007FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0007FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C
PIC18F6525/6621/8525/8621 24.2 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction.
PIC18F6525/6621/8525/8621 24.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming by the value written to the CONFIG2H Configuration register. FIGURE 24-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 16 16-to-1 MUX WDTEN Configuration bit WDTPS3:WDTPS0 SWDTEN bit WDT Time-out Note: TABLE 24-2: WDTPS3:WDTPS0 are bits in register CONFIG2H.
PIC18F6525/6621/8525/8621 24.3 Power-Down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or high-impedance).
PIC18F6525/6621/8525/8621 WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) FIGURE 24-2: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 24.
PIC18F6525/6621/8525/8621 TABLE 24-3: SUMMARY OF REGISTERS ASSOCIATED WITH CODE PROTECTION File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — WRT2 WRT1 WRT0 — — — EBTR2 EBTR1 EBTR0 — — — 30000Ah CONFIG6L — — — — 30000Bh CONFIG6H WRTD WRTB WRTC — 30000Ch CONFIG7L — — — — 30000Dh CONFIG7H — EBTRB — — (1) WRT3 — EBTR3 — (1) Legend: Shaded cells are unimp
PIC18F6525/6621/8525/8621 FIGURE 24-4: TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 000FFFh WRTB,EBTRB = 11 WRT0,EBTR0 = 01 PC = 003FFEh TBLWT* 003FFFh 004000h WRT1,EBTR1 = 11 007FFFh 008000h PC = 008FFEh WRT2,EBTR2 = 11 TBLWT* 00BFFFh 00C000h WRT3,EBTR3 = 11 00FFFFh Results: All table writes disabled to Block n whenever WRTn = 0.
PIC18F6525/6621/8525/8621 FIGURE 24-6: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 000FFFh PC = 003FFEh WRTB,EBTRB = 11 WRT0,EBTR0 = 10 TBLRD* 003FFFh 004000h WRT1,EBTR1 = 11 007FFFh 008000h WRT2,EBTR2 = 11 00BFFFh 00C000h WRT3,EBTR3 = 11 00FFFFh Results: Table reads permitted within Block n, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR. 24.4.
PIC18F6525/6621/8525/8621 24.5 ID Locations 24.8 Eight memory locations (200000h-200007h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are accessible during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected. 24.
PIC18F6525/6621/8525/8621 25.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC® instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations.
PIC18F6525/6621/8525/8621 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location.
PIC18F6525/6621/8525/8621 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
PIC18F6525/6621/8525/8621 TABLE 25-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f,
PIC18F6525/6621/8525/8621 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO — — n NOP NOP POP PUSH RCALL RESET RETFIE — — — — n RETLW RETURN SLEEP Note 1: 2: 3: 4: 5: 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Bran
PIC18F6525/6621/8525/8621 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtrac
PIC18F6525/6621/8525/8621 25.
PIC18F6525/6621/8525/8621 ADDWFC Add W and Carry bit to f ANDLW Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Operation: (W) + (f) + (C) dest Status Affected: N, Z Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: f [,d [,a] Encoding: 00da ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18F6525/6621/8525/8621 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a] Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 01da ffff ffff The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘d’ (default). If ‘a’ is ‘0’, the Access Bank will be selected. If ‘a’ is ‘1’, the BSR will not be overridden (default).
PIC18F6525/6621/8525/8621 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] Operation: 0 f Status Affected: None Encoding: 1001 f,b[,a] bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default).
PIC18F6525/6621/8525/8621 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’ (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0011 nnnn nnnn Encoding: 1110 If the Carry bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F6525/6621/8525/8621 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’ (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: n 0101 nnnn nnnn Encoding: 1110 If the Overflow bit is ‘0’, then the program will branch.
PIC18F6525/6621/8525/8621 BRA Unconditional Branch BSF Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F6525/6621/8525/8621 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skippe
PIC18F6525/6621/8525/8621 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Encoding: bbba ffff ffff Description: Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F6525/6621/8525/8621 BZ Branch if Zero CALL Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS; k PC<20:1> if s = 1 (W) WS; (STATUS) STATUSS; (BSR) BSRS Status Affected: None Status Affected: n Subroutine Call None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F6525/6621/8525/8621 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f; 1Z Status Affected: Z Encoding: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT; 000h WDT postscaler; 1 TO; 1 PD Status Affected: TO, PD Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F6525/6621/8525/8621 COMF Complement f Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: ( f ) dest Status Affected: N, Z Encoding: 0001 Description: CPFSEQ f [,d [,a] 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F6525/6621/8525/8621 CPFSGT Compare f with W, Skip if f > W CPFSLT Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) W); skip if (f) > (W) (unsigned comparison) Operation: (f) –W); skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: f [,a] 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by perf
PIC18F6525/6621/8525/8621 DAW Decimal Adjust W Register DECF Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4> Status Affected: Decrement f 0000 0000 Description: 0000 0000 ffff Words:
PIC18F6525/6621/8525/8621 DECFSZ Decrement f, Skip if 0 DCFSNZ Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest; skip if result = 0 Operation: (f) – 1 dest; skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff Decrement f, Skip if Not 0 Encoding: 0100 The contents of register ‘f’ are decremented.
PIC18F6525/6621/8525/8621 GOTO Unconditional Branch INCF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F6525/6621/8525/8621 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest; skip if result = 0 Operation: (f) + 1 dest; skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: INCFSZ f [,d [,a] 11da ffff ffff Increment f, Skip if Not 0 Encoding: 0100 The contents of register ‘f’ are incremented.
PIC18F6525/6621/8525/8621 IORLW Inclusive OR Literal with W IORWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. k W 0 f 255 d [0,1] a [0,1] Status Affected: N, Z Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: IORLW k 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F6525/6621/8525/8621 LFSR Load FSR MOVF Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 LFSR f,k 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F6525/6621/8525/8621 MOVFF Move f to f MOVLB Syntax: [ label ] Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) MOVFF fs,fd 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F6525/6621/8525/8621 MOVLW Move Literal to W MOVWF Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 MOVLW k 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W.
PIC18F6525/6621/8525/8621 MULLW Multiply Literal with W Syntax: [ label ] Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: MULLW MULWF k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected.
PIC18F6525/6621/8525/8621 NEGF Negate f Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: NEGF f [,a] 1 Cycles: 1 ffff Syntax: [ label ] Operands: None NOP Operation: No operation Status Affected: None 0000 1111 ffff 0000 xxxx Description: No operation.
PIC18F6525/6621/8525/8621 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: POP 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F6525/6621/8525/8621 RCALL Relative Call Syntax: [ label ] RCALL Operands: -1024 n 1023 Operation: (PC) + 2 TOS; (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: n 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n.
PIC18F6525/6621/8525/8621 RETFIE Return from Interrupt RETLW Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC; 1 GIE/GIEH or PEIE/GIEL if s = 1 (WS) W; (STATUSS) STATUS; (BSRS) BSR; PCLATU, PCLATH are unchanged Operation: k W; (TOS) PC; PCLATU, PCLATH are unchanged Status Affected: None Status Affected: RETFIE [s] Encoding: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: 1100 kkkk kkkk W is
PIC18F6525/6621/8525/8621 RETURN Return from Subroutine RLCF Syntax: [ label ] Syntax: [ label ] Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1 (WS) W; (STATUSS) STATUS; (BSRS) BSR; PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest; (f<7>) C; (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: RETURN [s] Rotate Left f through Carry Encoding: 0000 0001 001s 0011 Description: f [
PIC18F6525/6621/8525/8621 RLNCF Rotate Left f (No Carry) RRCF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest; (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest; (f<0>) C; (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a] ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F6525/6621/8525/8621 RRNCF Rotate Right f (No Carry) SETF Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest; (f<0>) dest<7> Status Affected: None Status Affected: f [,d [,a] Encoding: N, Z Encoding: 0100 Description: RRNCF Set f 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F6525/6621/8525/8621 SLEEP Enter Sleep Mode SUBFWB Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: 00h WDT; 0 WDT postscaler; 1 TO; 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: SLEEP TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
PIC18F6525/6621/8525/8621 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z SUBLW k Operands: 0 k 255 Operation: k – (W) W Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk SUBWF f [,d [,a] Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F6525/6621/8525/8621 SUBWFB Subtract W from f with Borrow SWAPF Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>; (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: SUBWFB 10da f [,d [,a] ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F6525/6621/8525/8621 TBLRD Table Read Syntax: [ label ] Operands: None TBLRD ( *; *+; *-; +*) Operation: if TBLRD* (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change if TBLRD*+ (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD*(Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR if TBLRD+* (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Prog
PIC18F6525/6621/8525/8621 TBLWT Table Write TBLWT Syntax: [ label ] Words: Operands: None Cycles: 2 Operation: if TBLWT* (TABLAT) Holding Register; TBLPTR – No Change if TBLWT*+ (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*(TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR if TBLWT+* (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Q Cycle Activity: TBLWT ( *; *+; *-; +*) Description: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of TBLPTR t
PIC18F6525/6621/8525/8621 TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] TSTFSZ f [,a] Operation: skip if f = 0 Status Affected: None Encoding: 0110 Description: ffff ffff If ‘f’ = 0, the next instruction, fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F6525/6621/8525/8621 XORWF Exclusive OR W with f Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 XORWF 10da f [,d [,a] ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F6525/6621/8525/8621 26.
PIC18F6525/6621/8525/8621 26.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.
PIC18F6525/6621/8525/8621 26.9 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18F6525/6621/8525/8621 26.14 PICSTART Plus Development Programmer 26.17 PICDEM 2 Plus Demonstration Board The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PIC devices up to 40 pins.
PIC18F6525/6621/8525/8621 26.20 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development.
PIC18F6525/6621/8525/8621 NOTES: DS39612C-page 322 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ........................................
PIC18F6525/6621/8525/8621 FIGURE 27-1: PIC18F6525/6621/8525/8621 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F6525/6621/8525/8621 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz (Extended) 40 MHz (Industrial) Frequency DS39612C-page 324 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 FIGURE 27-2: PIC18LF6X2X/8X2X VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF6525/6621/8525/8621 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V FMAX 4 MHz Frequency For PIC18F6525/6621 and PIC18F8525/8621 in Microcontroller mode: FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V; FMAX = 40 MHz, if VDDAPPMIN > 4.2V. For PIC18F8525/8621 in modes other than Microcontroller mode: FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.
PIC18F6525/6621/8525/8621 27.1 DC Characteristics: Supply Voltage PIC18F6525/6621/8525/8621 (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F6525/6621/8525/8621 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F6525/6621/8525/8621 27.2 DC Characteristics: Power-Down and Supply Current PIC18F6525/6621/8525/8621 (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F6525/6621/8525/8621 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F6525/6621/8525/8621 27.
PIC18F6525/6621/8525/8621 27.
PIC18F6525/6621/8525/8621 27.
PIC18F6525/6621/8525/8621 27.3 DC Characteristics: PIC18F6525/6621/8525/8621 (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions with TTL buffer VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V VDD 5.5V with Schmitt Trigger buffer RC3 and RC4 VSS VSS 0.2 VDD 0.
PIC18F6525/6621/8525/8621 27.3 DC Characteristics: PIC18F6525/6621/8525/8621 (Industrial, Extended) PIC18LF6X2X/8X2X (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic D080A OSC2/CLKO (RC mode) D083A VOH D090 D090A OSC2/CLKO (RC mode) D092A D150 VOD Units Conditions — 0.6 V IOL = 8.5 mA, VDD = 4.
PIC18F6525/6621/8525/8621 TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.
PIC18F6525/6621/8525/8621 FIGURE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 27-3: LOW-VOLTAGE DETECT CHARACTERISTICS LOW-VOLTAGE DETECT CHARACTERISTICS Param Symbol No. D420 D423 VLVD VBG Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Characteristic Min LVD Voltage on VDD LVV = 0000 transition high-to-low LVV = 0001 — 1.
PIC18F6525/6621/8525/8621 TABLE 27-4: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC Characteristics Param No. Sym Characteristic Min Typ† Max Units V Conditions Internal Program Memory Programming Specifications VPP Voltage on MCLR/VPP pin 9.00 — 13.25 D112 IPP Current into MCLR/VPP pin — — 300 A D113 IDDP Supply Current during Programming — — 1.
PIC18F6525/6621/8525/8621 27.4 27.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F6525/6621/8525/8621 27.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications, unless otherwise noted. Figure 27-4 specifies the load conditions for the timing specifications.
PIC18F6525/6621/8525/8621 27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 27-6: Param. No.
PIC18F6525/6621/8525/8621 TABLE 27-7: Param. No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) Sym Characteristic Min Typ† Max Units FOSC FSYS Oscillator Frequency Range On-Chip VCO System Frequency 4 16 — — 10 40 trc PLL Start-up Time (Lock Time) — — 2 ms CLK CLKO Stability (Jitter) -2 — +2 % Conditions MHz HS mode MHz HS mode † Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC18F6525/6621/8525/8621 Param No. Symbol Characteristic Min Typ Max Units ns 22† TINP INT pin High or Low Time TCY — — 23† TRBP RB7:RB4 Change INT High or Low Time TCY — — 24† TRCP RC7:RC4 Change INT High or Low Time 20 † Note 1: Conditions ns ns These parameters are asynchronous events not related to any internal clock edges. Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
PIC18F6525/6621/8525/8621 Param. No Symbol Characteristics 167 Tacc Address Valid to Data Valid 168 Toe OE to Data Valid 169 TalL2oeH ALE to OE 171 TalH2csL Chip Enable Active to ALE 171A TubL2oeH AD Valid to Chip Enable Active FIGURE 27-8: Min Typ Max Units 0.75 TCY – 25 — — ns — 0.5 TCY – 25 ns 0.625 TCY – 10 — 0.625 TCY + 10 ns — — 10 ns 0.
PIC18F6525/6621/8525/8621 Param. No Symbol Characteristics 171 TalH2csL Chip Enable Active to ALE 171A TubL2oeH AD Valid to Chip Enable Active FIGURE 27-9: Min Typ Max Units — — 10 ns 0.25 TCY – 20 — — ns RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 27-4 for load conditions.
PIC18F6525/6621/8525/8621 TABLE 27-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. No.
PIC18F6525/6621/8525/8621 TABLE 27-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param. Symbol No. 40 Characteristic Tt0H T0CKI High Pulse Width Min No prescaler Tt0L T0CKI Low Pulse Width No prescaler — ns 10 — ns 0.5 TCY + 20 — ns 10 — ns TCY + 10 — ns Greater of: 20 ns or TCY + 40 N — ns 0.
PIC18F6525/6621/8525/8621 TABLE 27-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL ECCP/CCP MODULES) Param. Symbol No. 50 51 TccL TccH Characteristic CCPx Input Low Time With prescaler CCPx Input High Time With prescaler CCPx Input Period 53 TccR CCPx Output Rise Time FIGURE 27-13: Units 0.5 TCY + 20 — ns PIC18F6525/6621/ 8525/8621 10 — ns PIC18LF6X2X/8X2X 20 — ns No prescaler TccP TccF Max No prescaler 52 54 Min CCPx Output Fall Time 0.
PIC18F6525/6621/8525/8621 TABLE 27-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8525/8621) Param. No. Symbol Characteristic TdtV2wrH Data In Valid before WR or CS (setup time) 62 63 TwrH2dtI WR or CS to Data–in PIC18F6525/6621/ Invalid (hold time) 8525/8621 PIC18LF6X2X/8X2X TrdL2dtV RD and CS to Data–out Valid 64 Min Max Units Conditions 20 25 — — ns ns Extended Temp.
PIC18F6525/6621/8525/8621 Param. No. Symbol Characteristic Min Max Units 100 — ns 1.
PIC18F6525/6621/8525/8621 TABLE 27-16: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 Symbol TscH 71A 72 TscL 72A Characteristic Min Max Units SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns 100 — ns 1.
PIC18F6525/6621/8525/8621 TABLE 27-17: EXAMPLE SPI™ MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param. No. Symbol Characteristic 70 TssL2scH, SS to SCK or SCK Input TssL2scL 71 TscH SCK Input High Time (Slave mode) TscL SCK Input Low Time (Slave mode) 71A 72 72A 73 Min Max TCY — ns 1.25 TCY + 30 — ns Single Byte 40 — ns Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns 100 — ns 1.
PIC18F6525/6621/8525/8621 FIGURE 27-17: EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit 6 - - - -1 LSb In 74 Note: Refer to Figure 27-4 for load conditions. TABLE 27-18: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F6525/6621/8525/8621 Param No. 82 83 Symbol TssL2doV Characteristic SDO Data Output Valid after SS Edge Min Max Units Conditions PIC18F6525/6621/ 8525/8621 — 50 ns PIC18LF6X2X/8X2X — 100 ns 1.5 TCY + 40 — ns TscH2ssH, SS after SCK Edge TscL2ssH Note 1: Requires the use of Parameter #73A. 2: Only if Parameter #71A and #72A are used.
PIC18F6525/6621/8525/8621 FIGURE 27-19: I2C™ BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 27-4 for load conditions. DS39612C-page 352 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 TABLE 27-20: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH TLOW 101 102 TR 103 TF Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — s PIC18F6525/6621/8525/ 8621 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s PIC18F6525/6621/8525/ 8621 must operate at a minimum of 10 MHz MSSP module 1.5 TCY — 100 kHz mode 4.7 — s PIC18F6525/6621/8525/ 8621 must operate at a minimum of 1.
PIC18F6525/6621/8525/8621 MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 27-20: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-21: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F6525/6621/8525/8621 TABLE 27-22: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18F6525/6621/8525/8621 FIGURE 27-22: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX1/CK1 pin 121 121 RC7/RX1/DT1 pin 120 Note: 122 Refer to Figure 27-4 for load conditions. TABLE 27-23: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. Symbol No.
PIC18F6525/6621/8525/8621 TABLE 27-25: A/D CONVERTER CHARACTERISTICS:PIC18F6525/6621/8525/8621 (INDUSTRIAL, EXTENDED) PIC18LF6X2X/8X2X (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units Conditions A01 NR Resolution — — — — 10 TBD bit bit VREF = VDD 3.0V VREF = VDD 3.0V A03 EIL Integral Linearity Error — — — — <±1 TBD LSb LSb VREF = VDD 3.0V VREF = VDD 3.0V A04 EDL Differential Linearity Error — — — — <±1 TBD LSb LSb VREF = VDD 3.0V VREF = VDD 3.
PIC18F6525/6621/8525/8621 FIGURE 27-24: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
PIC18F6525/6621/8525/8621 NOTES: 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 28.0 Note: DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC18F6525/6621/8525/8621 FIGURE 28-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 40 36 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 32 28 5.5V IDD (mA) 24 5.0V 20 4.5V 4.2V 16 12 8 4 0 4 5 6 7 8 9 10 9 10 FOSC (MHz) FIGURE 28-4: MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) 45 40 35 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 30 5.5V IDD (mA) 5.0V 25 4.
PIC18F6525/6621/8525/8621 FIGURE 28-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 5 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 4 5.0V 4.5V 4.0V 3 IDD (mA) 3.5V 3.0V 2 2.5V 2.0V 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) FIGURE 28-6: 7 5.5V 6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 5.0V 4.5V 5 4.0V IDD (mA) 4 3.
PIC18F6525/6621/8525/8621 FIGURE 28-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) , 1 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.9 5.5V 0.8 5.0V 4.5V IDD (mA) 0.7 4.0V 0.6 3.5V 0.5 3.0V 2.5V 0.4 2.0V 0.3 0.2 20 30 40 50 60 70 80 90 100 80 90 100 FOSC (kHz) MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) FIGURE 28-8: 6 5.
PIC18F6525/6621/8525/8621 FIGURE 28-9: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 36 5.5V 32 5.0V 28 4.5V 4.2V IDD (mA) 24 4.0V 20 16 3.5V 12 3.0V 8 4 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) FIGURE 28-10: 48 44 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +85°C) Minimum: mean – 3 (-40°C to +85°C) 40 5.
PIC18F6525/6621/8525/8621 FIGURE 28-11: TYPICAL AND MAXIMUM IT1OSC vs. VDD (TIMER1 AS SYSTEM CLOCK) 240 Typical: statistical mean @ 25°C Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) 220 200 180 160 IDD (uA) 140 120 100 80 Max (70°C) 60 Typ (25°C) 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-12: AVERAGE FOSC vs. VDD FOR VARIOUS Rs (RC MODE, C = 20 pF, TEMP = 25°C) 6,000 Operation above 4 MHz is not recomended. 5,000 3.3k 3.3 3.
PIC18F6525/6621/8525/8621 FIGURE 28-13: AVERAGE FOSC vs. VDD FOR VARIOUS Rs (RC MODE, C = 100 pF, TEMP = 25°C) 2,200 2,000 1,800 3.3 3.3kk 1,600 Freq (kHz) 1,400 5.1 5.1kk 1,200 1,000 800 10 10kk 600 400 200 100 100kk 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-14: AVERAGE FOSC vs. VDD FOR VARIOUS Rs (RC MODE, C = 300 pF, TEMP = 25°C) 800 700 3.3 3.3kk 600 5.1 5.1kk Freq (MHz) 500 400 300 10 10kk 200 100 100 100kk 0 2.0 2.5 3.0 3.5 4.0 4.
PIC18F6525/6621/8525/8621 FIGURE 28-15: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 1000 Max (-40°C to +125°C) 100 Max (85°C) IPD (uA) 10 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1 Typ (25°C) 0.1 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-16: TYPICAL AND MAXIMUM IBOR vs. VDD OVER TEMPERATURE, VBOR = 2.00-2.
PIC18F6525/6621/8525/8621 FIGURE 28-17: IT1OSC vs. VDD (SLEEP MODE, TIMER1 AND OSCILLATOR ENABLED) 80 Typical: statistical mean @ 25°C Maximum: mean + 3 (-10°C to +70°C) Minimum: mean – 3 (-10°C to +70°C) 70 Max (70°C) 60 IPD (uA) 50 40 30 20 Typ (25°C) 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-18: IPD vs.
PIC18F6525/6621/8525/8621 FIGURE 28-19: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD 40 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 35 Max (125°C) WDT Period (ms) 30 Max (85°C) 25 20 Typ (25°C) 15 10 Min (-40°C) 5 0 2.5 3.0 FIGURE 28-20: 3.5 4.0 VDD (V) 4.5 5.0 5.5 ILVD vs. VDD OVER TEMPERATURE, VLVD = 4.5-4.
PIC18F6525/6621/8525/8621 FIGURE 28-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.5 5.0 4.5 Max Max 4.0 Typ Typ(+25°C) (25C) VOH (V) 3.5 3.0 Min Min 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 28-22: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.0 2.5 2.0 VOH (V) Max Max 1.5 Typ Typ(+25°C) (25C) 1.0 Min Min 0.5 0.0 0 5 10 15 20 25 IOH (-mA) DS39612C-page 370 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 FIGURE 28-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.8 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.4 VOL (V) 1.2 1.0 Max Max 0.8 0.6 0.4 Typ (+25°C) Typ (25C) 0.2 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 28-24: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 2.
PIC18F6525/6621/8525/8621 FIGURE 28-25: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 3.5 VIH Max 3.0 2.5 VIN (V) VIH Min 2.0 VIL Max 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 28-26: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C) 1.
PIC18F6525/6621/8525/8621 MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C) FIGURE 28-27: 3.5 VIH Max Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 3.0 2.5 2.0 VIN (V) VVILILMax VIH Min 1.5 1.0 VIL Min 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C) FIGURE 28-28: 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.
PIC18F6525/6621/8525/8621 FIGURE 28-29: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VREFH (V) DS39612C-page 374 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 NOTES: 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18F6621 -I/PT e3 0410017 Example 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F6525/6621/8525/8621 29.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45° α A c φ L β A2 A1 (F) Units Dimension Limits n p MIN INCHES NOM 64 .020 16 .043 .039 .006 .024 .039 3.5 .472 .472 .
PIC18F6525/6621/8525/8621 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 p D1 D 2 1 B n CH x 45° A α c φ β L A2 A1 (F) Units Dimension Limits n p MIN INCHES NOM 80 .020 20 .043 .039 .004 .024 .039 3.5 .551 .551 .472 .472 .006 .009 .035 10 10 MAX MILLIMETERS* NOM 80 0.50 20 1.00 1.10 0.95 1.00 0.
PIC18F6525/6621/8525/8621 NOTES: 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 APPENDIX A: REVISION HISTORY Revision A (July 2003) Original data sheet for PIC18F6525/6621/8525/8621 family. APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (August 2004) This revision includes updates to the Electrical Specifications in Section 27.0, the DC and AC Characteristics Graphs and Tables in Section 28.0 have been added and includes minor corrections to the data sheet text.
PIC18F6525/6621/8525/8621 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC17C756 to a PIC18F8720. Not Applicable APPENDIX D: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e.
PIC18F6525/6621/8525/8621 APPENDIX E: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXXX) is provided in AN726, “PIC17CXXX to PIC18CXXX Migration.” This Application Note is available as Literature Number DS00726. DS39612C-page 382 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 NOTES: 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 INDEX A A/D .................................................................................... 233 Acquisition Requirements ......................................... 238 Acquisition Time........................................................ 238 ADCON0 Register..................................................... 233 ADCON1 Register..................................................... 233 ADCON2 Register..................................................... 233 ADRESH Register...
PIC18F6525/6621/8525/8621 Timer3....................................................................... 144 Timer3 (16-Bit Read/Write Mode) ............................. 144 Timer4....................................................................... 148 Watchdog Timer........................................................ 268 BN ..................................................................................... 284 BNC ..................................................................................
PIC18F6525/6621/8525/8621 Reading....................................................................... 81 Using ........................................................................... 82 Write Verify ................................................................. 82 Writing To.................................................................... 81 Data Memory....................................................................... 47 General Purpose Registers.........................................
PIC18F6525/6621/8525/8621 I I/O Ports ............................................................................ 103 I2C Mode Associated Registers ................................................ 212 General Call Address Support .................................. 196 Master Mode Operation .......................................................... 198 Master Mode Transmit Sequence ............................. 198 Read/Write Bit Information (R/W Bit) ................ 186, 187 Serial Clock (RC3/SCK/SCL) ...
PIC18F6525/6621/8525/8621 K Key Features Easy Migration .............................................................. 7 Expanded Memory ........................................................ 7 External Memory Interface ............................................ 7 Other Special Features ................................................. 7 L LFSR ................................................................................. 299 Low-Voltage Detect........................................................
PIC18F6525/6621/8525/8621 P Packaging ......................................................................... 373 Details ....................................................................... 374 Marking ..................................................................... 373 Parallel Slave Port (PSP) .......................................... 111, 128 Associated Registers ................................................ 130 RE0/AD8/RD/P2D Pin...............................................
PIC18F6525/6621/8525/8621 PORTE Analog Port Pins ....................................................... 128 Associated Registers ................................................ 116 Functions .................................................................. 116 LATE Register........................................................... 114 PORTE Register ....................................................... 114 PSP Mode Select (PSPMODE Bit) ................... 111, 128 RE0/AD8/RD/P2D Pin...................
PIC18F6525/6621/8525/8621 CONFIG7H (Configuration 7 High) ........................... 266 CONFIG7L (Configuration 7 Low)............................. 265 CVRCON (Comparator Voltage Reference Control) ........................................... 249 Device ID Register 2 ................................................. 266 DEVID1 (Device ID Register 1)................................. 266 ECCPxAS (ECCP Auto-Shutdown Control).............. 169 ECCPxDEL (PWM Configuration).............................
PIC18F6525/6621/8525/8621 Timer0 ............................................................................... 131 16-Bit Mode Timer Reads and Writes ....................... 133 Associated Registers ................................................ 133 Clock Source Edge Select (T0SE Bit)....................... 133 Clock Source Select (T0CS Bit) ................................ 133 Operation .................................................................. 133 Overflow Interrupt ...........................
PIC18F6525/6621/8525/8621 Slave Synchronization .............................................. 179 Slow Rise Time (MCLR Tied to VDD via 1 kResistor)................................................ 38 SPI Mode (Master Mode) .......................................... 178 SPI Mode (Slave Mode with CKE = 0) ...................... 180 SPI Mode (Slave Mode with CKE = 1) ...................... 180 Stop Condition Receive or Transmit Mode ............... 206 Synchronous Reception (Master Mode, SREN)...............
PIC18F6525/6621/8525/8621 DS39612C-page 394 2003-2013 Microchip Technology Inc.
PIC18F6525/6621/8525/8621 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC18F6525/6621/8525/8621 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18F6525/6621/8525/8621 PIC18F6525/6621/8525/8621 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Device PIC18F6525/6621/8525/8621(1), PIC18F6525/6621/8525/8621T(2); VDD range 4.2V to 5.5V PIC18LF6X2X/8X2X(1), PIC18LF6X2X/8X2XT(2); VDD range 2.0V to 5.
PIC18F6525/6621/8525/8621 DS39612C-page 398 2003-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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