Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 80 (12x12) 8-Bit 64 MHz I/O number 69

100

 2009-2011 Microchip Technology Inc. DS39957D-page 97

PIC18F87K90 FAMILY

TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY

Address

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

EF4h LCDCON LCDEN SLPEN WERR

—CS1CS0LMUX1LMUX0000- 0000

EF5h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000

EF6h LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 0000 0000

EF7h LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 0000 0000

EF8h LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000

EF9h LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000

EFAh LCDSE4 SE39 SE38 S37 SE36 SE35 SE34 SE33 SE32 0000 0000

EFBh LCDSE5

(2)

SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40 0000 0000

EFCh LCDRL LRLAP1 LRLAP0 LRLBP1 LRLBP0

— LRLAT2 LRLAT1 LRLAT0 0000 -000

EFDh LCDREF LCDIRE LCDIRS LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE 0000 0000

EFEh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000

EFFh SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000

F00h SSP2STAT SMP CKE D/A

PSR/WUA BF 0000 0000

F01h SSP2ADD MSSP Address Register in I

C™ Slave Mode. SSP1 Baud Rate Reload Register in I

C Master Mode 0000 0000

F02h SSP2BUF MSSP Receive Buffer/Transmit Register xxxx xxxx

F03h T4CON

— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000

F04h PR4 Timer4 Period Register 0000 0000

F05h TMR4 Timer4 Register 1111 1111

F06h CCP7CON

— — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 --00 0000

F07h CCPR7L Capture/Compare/PWM Register 7 Low Byte xxxx xxxx

F08h CCPR7H Capture/Compare/PWM Register7 High Byte xxxx xxxx

F09h CCP6CON

— — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 --00 0000

F0Ah CCPR6L Capture/Compare/PWM Register 6 Low Byte xxxx xxxx

F0Bh CCPR6H Capture/Compare/PWM Register6 High Byte xxxx xxxx

F0Ch CCP5CON

— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000

F0Dh CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx

F0Eh CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx

F0Fh CCP4CON

— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000

F10h CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx

F11h CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx

F12h T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/

T5DONE

T5GVAL T5GSS1 T5GSS0 0000 0000

F13h T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC

RD16 TMR5ON 0000 0000

F14h TMR5L Timer5 Register Low Byte 0000 0000

F15h TMR5H Timer5 Register High Byte xxxx xxxx

F16h PMD3

CCP10MD

(3)

CCP9MD

(3)

CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD

TMR12MD

(3)

0000 0000

F17h PMD2

TMR10MD

(3)

TMR8MD TMR7MD

(3)

TMR6MD TMR5MD CMP3MD CMP2MD CMP1MD 0000 0000

F18h PMD1

— CTMUMDRTCCMDTMR4MDTMR3MDTMR2MDTMR1MD — -000 000-

F19h PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD 0000 0000

F1Ah PSTR3CON CMPL1 CMPL0

— STRSYNC STRD STRC STRB STRA 00-0 0001

F1Bh PSTR2CON CMPL1 CMPL0

— STRSYNC STRD STRC STRB STRA 00-0 0001

F1Ch TXREG2 Transmit Data FIFO xxxx xxxx

F1Dh RCREG2 Receive Data FIFO 0000 0000

F1Eh SPBRG2 USART2 Baud Rate Generator Low Byte 0000 0000

F1Fh SPBRGH2 USART2 Baud Rate Generator High Byte 0000 0000

F20h BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16

— WUE ABDEN 0100 0-00

F21h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010

F22h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x

F23h ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 1111 1111

Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.

2: Unimplemented in 64-pin devices (PIC18F6XK90).

3: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).