Datasheet

PIC18F87K90 FAMILY
DS39957D-page 388  2009-2011 Microchip Technology Inc.
TABLE 23-2: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 75
PIR1
—ADIFRC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF 77
PIE1
—ADIERC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE 77
IPR1
—ADIPRC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP 77
ADRESH A/D Result Register High Byte 76
ADRESL A/D Result Register Low Byte 76
ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
76
ADCON1 TRIGSEL1 TRIGSEL0 VCFG1 VCFG0 VNCFG CHSN2 CHSN1 CHSN0 76
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 76
ANCON0 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 81
ANCON1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 81
ANCON2 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 81
CCP2CON
P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 80
PORTA
RA7
(2)
RA6
(2)
RA5 RA4 RA3 RA2 RA1 RA0 78
TRISA
TRISA7
(2)
TRISA6
(2)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 78
PORTF
RF7RF6RF5RF4RF3RF2RF1 — 78
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1
— 78
PORTG
— — RG5
(3)
RG4 RG3 RG2 RG1 RG0 78
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 78
PORTH
(1)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 78
TRISH
(1)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 78
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: This register is not implemented on 64-pin devices.
2: These bits are available only in certain oscillator modes, when the OSC2 Configuration bit = 0. If that
Configuration bit is cleared, this signal is not implemented.
3: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is
unimplemented.