Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 269

PIC18F87K90 FAMILY

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R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1

CMPL1 CMPL0

— STRSYNC STRD STRC STRB STRA

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits

00 = See STRD:STRA

01 = PA and PB are selected as the complementary output pair

10 = PA and PC are selected as the complementary output pair

11 = PA and PD are selected as the complementary output pair

bit 5 Unimplemented: Read as ‘0’

bit 4 STRSYNC: Steering Sync bit

1 = Output steering update occurs on the next PWM period

0 = Output steering update occurs at the beginning of the instruction cycle boundary

bit 3 STRD: Steering Enable Bit D

1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxD pin is assigned to a PORT pin

bit 2 STRC: Steering Enable Bit C

1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxC pin is assigned to a PORT pin

bit 1 STRB: Steering Enable Bit B

1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxB pin is assigned to a PORT pin

bit 0 STRA: Steering Enable Bit A

1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>

0 = PxA pin is assigned to a PORT pin

Note 1: The PWM Steering mode is available only when the CCPxCON register bits, CCPxM<3:2> = 11 and

PxM<1:0> = 00.