Datasheet

 2009-2011 Microchip Technology Inc. DS39957D-page 175
PIC18F87K90 FAMILY
11.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISG and LATG.
PORTG is multiplexed with EUSART, LCD and
CCP/ECCP/Analog/Comparator/RTCC/Timer input func-
tions (Table 11-14). When operating as I/O, all PORTG
pins have Schmitt Trigger input buffers. The open-drain
functionality for the CCPx and UART can be configured
using ODCONx.
RG4 is multiplexed with LCD segment drives controlled
by bits in the LCDSE2 register and as the
RG4/SEG26/RTCC/T7CKI/T5G/CCP5/AN16/P1D/C3INC
pin. The I/O port function is only available when the
segments are disabled.
The RG5 pin is multiplexed with the MCLR
pin and is
available only as an input port. To configure this port for
input only, set the MCLRE pin (CONFIG3H<7>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
EXAMPLE 11-7: INITIALIZING PORTG
CLRF PORTG ; Initialize PORTG by
; clearing output
; data latches
BCF CM1CON, CON ; disable
; comparator 1
CLRF LATG ; Alternate method
; to clear output
; data latches
BANKSEL ANCON2
MOVLW 0F0h ; make AN16 to AN19
; digital
MOVWF ANCON2
MOVLW
04h ; Value used to
; initialize data
; direction
MOVWF
TRISG ; Set RG1:RG0 as
; outputs
; RG2 as input
;
RG4:RG3 as inputs
TABLE 11-14: PORTG FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/ECCP3/
P3A
RG0 0 O DIG LATG<0> data output.
1 I ST PORTG<0> data input.
ECCP3 0 O DIG ECCP3 compare output and ECCP3 PWM output; takes priority over
port data.
1 I ST ECCP3 capture input.
P3A 0 O — ECCP3 PWM Output A. May be configured for tri-state during
Enhanced PWM shutdown events.
RG1/TX2/CK2/
AN19/C3OUT
RG1 0 O DIG LATG<1> data output.
1 I ST PORTG<1> data input.
TX2 1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
CK2 1 O DIG Synchronous serial data input (EUSART module); user must configure
as an input.
1 I ST Synchronous serial clock input (EUSART module).
AN19 1 I ANA A/D Input Channel 19. Default input configuration on POR. Does not
affect digital output.
C3OUT x O DIG Comparator 3 output.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).