Datasheet
PIC18F87K90 FAMILY
DS39957D-page 102 2009-2011 Microchip Technology Inc.
FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ----
FE0h BSR
— — — — Bank Select Register ---- 0000
FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx
FE2h FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- xxxx
FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
---- ----
FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ----
FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) ---- ----
FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ----
FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ----
FE8h WREG Working Register xxxx xxxx
FE9h FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx
FEAh FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- xxxx
FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
---- ----
FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ----
FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ----
FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ----
FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ----
FF0h INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000
FF1h INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111
FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x
FF3h PRODL Product Register Low Byte xxxx xxxx
FF4h PRODH Product Register High Byte xxxxxxxx
FF5h TABLAT Program Memory Table Latch 0000 0000
FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000
FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000
FF8h TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000
FF9h PCL PC Low Byte (PC<7:0>) 0000 0000
FFAh PCLATH Holding Register for PC<15:8> 0000 0000
FFBh PCLATU
— — — Holding Register for PC<20:16> ---0 0000
FFCh STKPTR STKFUL STKUNF
— Return Stack Pointer uu-0 0000
FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000
FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000
FFFh TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000
TABLE 6-2: PIC18F87K90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Note 1: This bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented in 64-pin devices (PIC18F6XK90).
3: Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).