Datasheet

 2010 Microchip Technology Inc. DS39770C-page 77
PIC18F85J90 FAMILY
SPBRG1 EUSART Baud Rate Generator 0000 0000 59, 240
RCREG1 EUSART Receive Register 0000 0000 59, 248
TXREG1 EUSART Transmit Register 0000 0000 59, 246
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 59, 236
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 59, 237
LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 59, 165
LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 0000 0000 59, 166
LCDCON LCDEN SLPEN WERR
—CS1CS0LMUX1LMUX0000- 0000 59, 164
EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 59, 88
EECON1
— — — FREE WRERR WREN WR — ---0 x00- 59, 89
IPR3
— LCDIP RC2IP TX2IP — CCP2IP CCP1IP — -111 -11- 60, 112
PIR3
— LCDIF RC2IF TX2IF — CCP2IF CCP1IF — -000 -00- 60, 106
PIE3
— LCDIE RC2IE TX2IE — CCP2IE CCP1IE — -000 -00- 60, 109
IPR2 OSCFIP CMIP
— — BCLIP LVDIP TMR3IP — 11-- 111- 60, 111
PIR2 OSCFIF CMIF
— — BCLIF LVDIF TMR3IF — 00-- 000- 60, 105
PIE2 OSCFIE CMIE
— — BCLIE LVDIE TMR3IE — 00-- 000- 60, 108
IPR1
— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP -111 1-11 60, 110
PIR1
— ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF-000 0-00 60, 104
PIE1
— ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE -000 0-00 60, 107
OSCTUNE INTSRC PLLEN
(4)
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 0000 37, 60
TRISJ
(2)
TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 60, 136
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 60, 134
TRISG SPIOD CCP2OD CCP1OD TRISG4TRISG3TRISG2TRISG1 TRISG0 0001 1111 60, 132
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1
— 1111 111- 60, 130
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3
— TRISE1 TRISE0 1111 1-11 60, 127
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 60, 125
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 60, 123
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 60, 120
TRISA TRISA7
(5)
TRISA6
(5)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 60, 117
LATJ
(2)
LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx xxxx 60, 136
LATH
(2)
LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 60, 134
LATG U2OD U1OD
— LATG4 LATG3 LATG2 LATG1 LATG0 00-x xxxx 60, 132
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1
— xxxx xxx- 60, 130
LATE LATE7 LATE6 LATE5 LATE4 LATE3
—LATE1LATE0xxxx x-xx 60, 127
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 60, 125
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 60, 123
LATB LATB7LATB6LATB5LATB4LATB3LATB2LATB1LATB0xxxx xxxx 60, 120
LATA LATA7
(5)
LATA6
(5)
LATA5LATA4LATA3LATA2LATA1LATA0xxxx xxxx 60, 117
TABLE 6-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier” for details.
5: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’.