Datasheet

Table Of Contents
2010 Microchip Technology Inc. DS39770C-page 75
PIC18F85J90 FAMILY
TABLE 6-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page
TOSU
Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 57, 65
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 57, 65
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 57, 65
STKPTR STKFUL STKUNF
Return Stack Pointer uu-0 0000 57, 66
PCLATU
—bit 21
(1)
Holding Register for PC<20:16> ---0 0000 57, 65
PCLATH Holding Register for PC<15:8> 0000 0000 57, 65
PCL PC Low Byte (PC<7:0>) 0000 0000 57, 65
TBLPTRU
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 57, 90
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 57, 90
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 57, 90
TABLAT Program Memory Table Latch 0000 0000 57, 90
PRODH Product Register High Byte xxxx xxxx 57, 97
PRODL Product Register Low Byte xxxx xxxx 57, 97
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 57, 101
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 57, 102
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 57, 103
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 57, 81
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 57, 82
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 57, 82
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 57, 82
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 57, 82
FSR0H
Indirect Data Memory Address Pointer 0 High ---- xxxx 57, 81
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 57, 81
WREG Working Register xxxx xxxx 57
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 57, 81
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 57, 82
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 57, 82
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 57, 82
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 57, 82
FSR1H
Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 58, 81
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 58, 81
BSR
Bank Select Register ---- 0000 58, 70
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 58, 81
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 58, 82
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 58, 82
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 58, 82
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 58, 82
FSR2H
Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 58, 81
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 58, 81
STATUS
—NOVZDCC---x xxxx 58, 79
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, do not modify
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: These registers and/or bits are available only on 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset states shown
are for 80-pin devices.
3: Alternate names and definitions for these bits when the MSSP module is operating in I
2
C™ Slave mode. See Section 17.4.3.2 “Address
Masking” for details.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 3.4.3 “PLL
Frequency Multiplier for details.
5: RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default
clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as0’.