Datasheet

PIC18F85J90 FAMILY
DS39770C-page 400  2010 Microchip Technology Inc.
APPENDIX B: MIGRATION
BETWEEN HIGH-END
DEVICE FAMILIES
Devices in the PIC18F85J90 and PIC18F8490 families
are very similar in their functions and feature sets.
However, there are some potentially important differ-
ences which should be considered when migrating an
application across device families to achieve a new
design goal. These are summarized in Table B-1. The
areas of difference, which could be a major impact on
migration, are discussed in greater detail later in this
section.
TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F8490 AND PIC18F85J90 FAMILIES
Characteristic PIC18F85J90 Family PIC18F8490 Family
Operating Frequency 40 MHz @ 2.35V 40 MHz @ 4.2V
Supply Voltage 2.0V-3.6V, Dual Voltage Requirement 2.0V-5.5V
Operating Current Low Lower
Program Memory Size (maximum) 32 Kbytes 16 Kbytes
Program Memory Endurance 1,000 Write/Erase Cycles (typical) 100,000 Write/Erase Cycles (typical)
Program Memory Retention 20 Years (minimum) 40 Years (minimum)
Programming Time (Normalized) 43.8 s/byte (2.8 ms/64-byte block) 15.6 s/byte (1 ms/64-byte block)
I/O Sink/Source at 25 mA PORTB and PORTC Only All Ports
Input Voltage Tolerance on I/O Pins 5.5V on Digital Only Pins V
DD on All I/O Pins
I/O 67 66
LCD Outputs (maximum pixels,
segments x commons)
192 192
LCD Bias Generation 4 Modes 1 Mode
LCD Voltage Regulator Implemented; Includes Voltage Boost Not Available
Pull-ups PORTB, PORTD, PORTE
and PORTJ
PORTB
Open-Drain Output Option Available on USARTs, SPI and CCP
Output Pins
Not Available
Oscillator Options Limited Primary Options (EC, HS,
PLL); Flexible Internal Oscillator
(INTOSC and INTRC)
More Primary Options (EC, HS, XT,
LP, RC, PLL); Flexible Internal
Oscillator (INTOSC and INTRC)
Programming Entry Low Voltage, Key Sequence V
PP and LVP
Code Protection Single Block, All or Nothing Multiple Code Protection Blocks
Configuration Words Stored in Last 4 Words of
Program Memory space
Stored in Configuration Space,
Starting at 300000h
Start-up Time from Sleep
200 s (typical)
10 s (typical)
10 s (typical) with
Voltage Regulator Disabled
Power-up Timer Always on Configurable
Data EEPROM Use Self-Programming Not Available
BOR Simple BOR with Voltage Regulator Separate Programmable BOR
LVD Integrated with Voltage Regulator Separate Programmable Module
A/D Channels 12 12
A/D Calibration Self-Calibration Feature Software Look-up Table
In-Circuit Emulation Not available Available