Datasheet

PIC18F85J90 FAMILY
DS39770C-page 40  2010 Microchip Technology Inc.
3.4.2 EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an exter-
nal clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3: EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available.
FIGURE 3-4: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
3.4.3 PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency
oscillator circuit, or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals, or users who require higher
clock speeds from an internal oscillator. For these
reasons, the HSPLL and ECPLL modes are available.
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external oscil-
lating source to produce frequencies up to 40 MHz.
The PLL is enabled by programming the FOSC<2:0>
Configuration bits (CONFIG2L<2:0>) to either ‘110’
(for ECPLL) or ‘100’ (for HSPLL). In addition, the
PLLEN bit (OSCTUNE<6>) must also be set. Clearing
PLLEN disables the PLL, regardless of the chosen
oscillator configuration. It also allows additional flexibil-
ity for controlling the application’s clock speed in
software.
FIGURE 3-5: PLL BLOCK DIAGRAM
OSC1/CLKI
OSC2/CLKO
F
OSC/4
Clock from
Ext. System
PIC18F85J90
or RA6
OSC1
OSC2
Open
Clock from
Ext. System
PIC18F85J90
(HS Mode)
MUX
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
F
IN
FOUT
SYSCLK
Phase
Comparator
HSPLL or ECPLL (CONFIG2L)
4
HS or EC
Mode