Datasheet

PIC18F85J90 FAMILY
DS39770C-page 384  2010 Microchip Technology Inc.
FIGURE 26-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input 3 TCY —ns
70A T
SSL2WB SS to Write to SSPBUF 3 TCY —ns
71 T
SCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single byte 40 — ns (Note 1)
72 TSCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 40 — ns
75 T
DOR SDO Data Output Rise Time — 25 ns
76 T
DOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS  to SDO Output High-Impedance 10 50 ns
78 T
SCR SCK Output Rise Time (Master mode) — 25 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SS
 after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
78
79
80
79
78
MSb LSb
bit 6 - - - - - - 1
bit 6 - - - - 1 LSb In
83
Note: Refer to Figure 26-3 for load conditions.
MSb In