Datasheet

 2010 Microchip Technology Inc. DS39770C-page 37
PIC18F85J90 FAMILY
3.3 Clock Sources and
Oscillator Switching
Essentially, PIC18F85J90 family devices have three
independent clock sources:
• Primary oscillators
• Secondary oscillators
• Internal oscillator
The primary oscillators can be thought of as the main
device oscillators. These are any external oscillators
connected to the OSC1 and OSC2 pins, and include
the External Crystal and Resonator modes and the
External Clock modes. In some circumstances, the
internal oscillator block may be considered a primary
oscillator. The particular mode is defined by the FOSC
Configuration bits. The details of these modes are
covered in Section 3.4 “External Oscillator Modes”.
The secondary oscillators are external clock sources
that are not connected to the OSC1 or OSC2 pins.
These sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F85J90 family devices offer the Timer1 oscillator
as a secondary oscillator source. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock. The Timer1
oscillator is discussed in greater detail in Section 12.3
“Timer1 Oscillator”
In addition to being a primary clock source in some
circumstances, the internal oscillator is available as a
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor. The internal oscillator block is discussed in
more detail in Section 3.5 “Internal Oscillator
Block”.
The PIC18F85J90 family includes features that allow
the device clock source to be switched from the main
oscillator, chosen by device configuration, to one of the
alternate clock sources. When an alternate clock
source is enabled, various power-managed operating
modes are available.
REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN
(1)
TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived from INTRC 31 kHz oscillator
bit 6 PLLEN: Frequency Multiplier PLL Enable bit
(1)
1 = PLL enabled
0 = PLL disabled
bit 5-0 TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits
011111 = Maximum frequency
• •
• •
000001
000000 = Center frequency. Fast RC oscillator is running at the calibrated frequency.
111111
• •
• •
100000 = Minimum frequency
Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and reads
as ‘0’.