Datasheet

PIC18F85J90 FAMILY
DS39770C-page 262  2010 Microchip Technology Inc.
19.3 AUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA2<4>). In this mode, the
AUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip, dedicated, 8-bit Baud Rate Generator can be
used to derive standard baud rate frequencies from the
oscillator.
The AUSART transmits and receives the LSb first. The
AUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA2<2>). Parity is not supported by the
hardware but can be implemented in software and
stored as the 9th data bit.
When operating in Asynchronous mode, the AUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
19.3.1 AUSART ASYNCHRONOUS
TRANSMITTER
The AUSART transmitter block diagram is shown in
Figure 19-1. The heart of the transmitter is the Transmit
(Serial) Shift register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG2. The TXREG2 register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG2 register (if available).
Once the TXREG2 register transfers the data to the
TSR register (occurs in one T
CY), the TXREG2 register
is empty and the TX2IF flag bit (PIR3<4>) is set. This
interrupt can be enabled or disabled by setting or
clearing the interrupt enable bit, TX2IE (PIE3<4>).
TX2IF will be set regardless of the state of TX2IE; it
cannot be cleared in software. TX2IF is also not
cleared immediately upon loading TXREG2, but
becomes valid in the second instruction cycle following
the load instruction. Polling TX2IF immediately
following a load of TXREG2 will return invalid results.
While TX2IF indicates the status of the TXREG2
register, another bit, TRMT (TXSTA2<1>), shows the
status of the TSR register. TRMT is a read-only bit
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1. Initialize the SPBRG2 register for the appropriate
baud rate. Set or clear the BRGH bit, as required,
to achieve the desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If interrupts are desired, set enable bit, TX2IE.
4. If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit, TXEN,
which will also set bit, TX2IF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Load data to the TXREG2 register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 19-1: AUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit, TX2IF, is set when enable bit,
TXEN, is set.
TX2IF
TX2IE
Interrupt
TXEN
Baud Rate CLK
SPBRG2
Baud Rate Generator
TX9D
MSb
LSb
Data Bus
TXREG2 Register
TSR Register
(8)
0
TX9
TRMT
SPEN
TX2 pin
Pin Buffer
and Control
8
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