Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 80 (12x12) 8-Bit 40 MHz I/O number 67

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Table Of Contents

Low-Power Features:
LCD Driver Module Features:
Special Microcontroller Features:
Flexible Oscillator Structure:
Peripheral Highlights:
Pin Diagrams
Pin Diagrams (Continued)
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 Core Features
- 1.2 LCD Driver
- 1.3 Other Special Features
- 1.4 Details on Individual Family Members
2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers
- 2.1 Basic Connection Requirements
  - FIGURE 2-1: Recommended Minimum connections
- 2.2 Power Supply Pins
  - 2.2.1 Decoupling Capacitors
  - 2.2.2 Tank Capacitors
- 2.3 Master Clear (MCLR) Pin
  - FIGURE 2-2: Example of MCLR Pin Connections
- 2.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)
  - FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap
- 2.5 ICSP Pins
- 2.6 External Oscillator Pins
- 2.7 Unused I/Os
  - FIGURE 2-4: Suggested Placement of the Oscillator Circuit
3.0 Oscillator Configurations
- 3.1 Oscillator Types
  - FIGURE 3-1: PIC18F85J90 family Clock Diagram
- 3.2 Control Registers
  - Register 3-1: OSCCON: Oscillator Control Register
  - Register 3-2: OSCTUNE: Oscillator Tuning Register
- 3.3 Clock Sources and Oscillator Switching
  - 3.3.1 Clock Source Selection
  - 3.3.2 Oscillator Transitions
- 3.4 External Oscillator Modes
- 3.5 Internal Oscillator Block
- 3.6 Effects of Power-Managed Modes on the Various Clock Sources
- 3.7 Power-up Delays
  - TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode
4.0 Power-Managed Modes
- 4.1 Selecting Power-Managed Modes
- 4.2 Run Modes
- 4.3 Sleep Mode
- 4.4 Idle Modes
- 4.5 Exiting Idle and Sleep Modes
5.0 Reset
- 5.1 RCON Register
  - FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit
  - Register 5-1: RCON: Reset Control Register
- 5.2 Master Clear (MCLR)
- 5.3 Power-on Reset (POR)
- 5.4 Brown-out Reset (BOR)
  - FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
  - 5.4.1 Detecting BOR
- 5.5 Configuration Mismatch (CM)
- 5.6 Power-up Timer (PWRT)
  - 5.6.1 Time-out Sequence
- 5.7 Reset State of Registers
  - TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register
  - TABLE 5-2: Initialization Conditions for All Registers
6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
  - FIGURE 7-1: Table Read Operation
  - FIGURE 7-2: Table Write Operation
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
  - FIGURE 7-4: Reads from Flash Program Memory
  - EXAMPLE 7-1: Reading a Flash Program Memory Word
- 7.4 Erasing Flash Program Memory
  - 7.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 7-2: Erasing a Flash Program Memory Block
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
  - TABLE 7-2: Registers Associated with Program Flash Memory
8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
9.0 Interrupts
- FIGURE 9-1: PIC18F85J90 family Interrupt Logic
- 9.1 INTCON Registers
- 9.2 PIR Registers
- 9.3 PIE Registers
- 9.4 IPR Registers
- 9.5 RCON Register
  - Register 9-13: RCON: Reset Control Register
- 9.6 INTx Pin Interrupts
- 9.7 TMR0 Interrupt
- 9.8 PORTB Interrupt-on-Change
- 9.9 Context Saving During Interrupts
  - EXAMPLE 9-1: Saving STATUS, WREG and BSR Registers in RAM
10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 I/O Port Pin Capabilities
- 10.2 PORTA, TRISA and LATA Registers
- 10.3 PORTB, TRISB and LATB Registers
- 10.4 PORTC, TRISC and LATC Registers
- 10.5 PORTD, TRISD and LATD Registers
- 10.6 PORTE, TRISE and LATE Registers
- 10.7 PORTF, LATF and TRISF Registers
- 10.8 PORTG, TRISG and LATG Registers
- 10.9 PORTH, LATH and TRISH Registers
- 10.10 PORTJ, TRISJ and LATJ Registers
11.0 Timer0 Module
- Register 11-1: T0CON: Timer0 Control Register
- 11.1 Timer0 Operation
- 11.2 Timer0 Reads and Writes in 16-Bit Mode
  - FIGURE 11-1: Timer0 Block Diagram (8-Bit Mode)
  - FIGURE 11-2: Timer0 Block Diagram (16-Bit Mode)
- 11.3 Prescaler
  - 11.3.1 Switching Prescaler Assignment
- 11.4 Timer0 Interrupt
  - TABLE 11-1: Registers Associated with Timer0
12.0 Timer1 Module
- Register 12-1: T1CON: Timer1 Control Register
- 12.1 Timer1 Operation
  - FIGURE 12-1: Timer1 Block Diagram (8-Bit Mode)
  - FIGURE 12-2: Timer1 Block Diagram (16-Bit Read/Write Mode)
- 12.2 Timer1 16-Bit Read/Write Mode
- 12.3 Timer1 Oscillator
- 12.4 Timer1 Interrupt
- 12.5 Resetting Timer1 Using the CCP Special Event Trigger
- 12.6 Using Timer1 as a Real-Time Clock
  - EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
13.0 Timer2 Module
- 13.1 Timer2 Operation
  - Register 13-1: T2CON: Timer2 Control Register
- 13.2 Timer2 Interrupt
- 13.3 Timer2 Output
  - FIGURE 13-1: Timer2 Block Diagram
  - TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
14.0 Timer3 Module
- Register 14-1: T3CON: Timer3 Control Register
- 14.1 Timer3 Operation
  - FIGURE 14-1: Timer3 Block Diagram (8-Bit Mode)
  - FIGURE 14-2: Timer3 Block Diagram (16-Bit Read/Write Mode)
- 14.2 Timer3 16-Bit Read/Write Mode
- 14.3 Using the Timer1 Oscillator as the Timer3 Clock Source
- 14.4 Timer3 Interrupt
- 14.5 Resetting Timer3 Using the CCP Special Event Trigger
  - TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
15.0 Capture/Compare/PWM (CCP) Modules
- Register 15-1: CCPxCON: CCPx Control Register (CCP1, CCP2 Modules)
- 15.1 CCP Module Configuration
- 15.2 Capture Mode
- 15.3 Compare Mode
- 15.4 PWM Mode
16.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 16-1: LCD Driver Module Block Diagram
- 16.1 LCD Registers
  - 16.1.1 LCD Control Registers
  - 16.1.2 LCD Data Registers
    - Register 16-4: LCDDATAx: LCD Data Registers
    - TABLE 16-2: LCDDATA Registers and Bits for Segment and COM Combinations
- 16.2 LCD Clock Source
  - 16.2.1 LCD Voltage Regulator Clock Source
  - 16.2.2 Clock sOURCE cONSIDERATIONS
    - FIGURE 16-2: LCD Clock Generation
- 16.3 LCD Bias Generation
- 16.4 LCD Multiplex Types
  - TABLE 16-3: PORTE<6:4> Function
- 16.5 Segment Enables
- 16.6 Pixel Control
- 16.7 LCD Frame Frequency
  - TABLE 16-4: Frame Frequency Formulas
  - TABLE 16-5: Approximate Frame Frequency (in Hz) for LP Prescaler Settings
- 16.8 LCD Waveform Generation
- 16.9 LCD Interrupts
  - FIGURE 16-17: Example Waveforms and Interrupt Timing in Quarter Duty Cycle Drive
- 16.10 Operation During Sleep
  - 16.10.1 Using the LCD Regulator During Sleep
    - FIGURE 16-18: Sleep Entry/Exit When SLPEN = 1 or CS<1:0> = 00
- 16.11 Configuring the LCD Module
  - TABLE 16-6: Registers Associated with LCD Operation
17.0 Master Synchronous Serial Port (MSSP) Module
- 17.1 Master SSP (MSSP) Module Overview
- 17.2 Control Registers
- 17.3 SPI Mode
- 17.4 I2C Mode
18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 18.1 Control Registers
- 18.2 EUSART Baud Rate Generator (BRG)
- 18.3 EUSART Asynchronous Mode
- 18.4 EUSART Synchronous Master Mode
  - 18.4.1 EUSART Synchronous Master Transmission
  - 18.4.2 EUSART Synchronous Master Reception
    - FIGURE 18-13: Synchronous Reception (Master Mode, SREN)
    - TABLE 18-8: Registers Associated with Synchronous Master Reception
- 18.5 EUSART Synchronous Slave Mode
  - 18.5.1 EUSART Synchronous Slave Transmit
    - TABLE 18-9: Registers Associated with Synchronous Slave Transmission
  - 18.5.2 EUSART Synchronous Slave Reception
    - TABLE 18-10: Registers Associated with Synchronous Slave Reception
19.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
- 19.1 Control Registers
  - Register 19-1: TXSTA2: AUSART Transmit Status and Control Register
  - Register 19-2: RCSTA2: ausart Receive Status and Control Register
- 19.2 AUSART Baud Rate Generator (BRG)
  - 19.2.1 Operation in Power-Managed Modes
  - 19.2.2 Sampling
- 19.3 AUSART Asynchronous Mode
- 19.4 AUSART Synchronous Master Mode
  - 19.4.1 AUSART Synchronous Master Transmission
  - 19.4.2 AUSART Synchronous Master Reception
    - FIGURE 19-8: Synchronous Reception (Master Mode, SREN)
    - TABLE 19-7: Registers Associated with Synchronous Master Reception
- 19.5 AUSART Synchronous Slave Mode
  - 19.5.1 AUSART Synchronous Slave Transmit
    - TABLE 19-8: Registers Associated with Synchronous Slave Transmission
  - 19.5.2 AUSART Synchronous Slave Reception
    - TABLE 19-9: Registers Associated with Synchronous Slave Reception
20.0 10-bit Analog-to-Digital Converter (A/D) Module
- Register 20-1: ADCON0: A/D Control Register 0
- Register 20-2: ADCON1: A/D Control Register 1
- Register 20-3: ADCON2: A/D Control Register 2
- FIGURE 20-1: A/D Block Diagram(1,2)
- FIGURE 20-2: Analog Input Model
- 20.1 A/D Acquisition Requirements
- 20.2 Selecting and Configuring Automatic Acquisition Time
- 20.3 Selecting the A/D Conversion Clock
  - TABLE 20-1: Tad vs. Device Operating Frequencies
- 20.4 Configuring Analog Port Pins
- 20.5 A/D Conversions
- 20.6 Use of the CCP2 Trigger
  - FIGURE 20-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)
  - FIGURE 20-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)
- 20.7 A/D Converter Calibration
- 20.8 Operation in Power-Managed Modes
  - TABLE 20-2: Summary of A/D Registers
21.0 Comparator Module
- Register 21-1: CMCON: Comparator Module Control Register
- 21.1 Comparator Configuration
  - FIGURE 21-1: Comparator I/O Operating Modes
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
  - FIGURE 21-3: Comparator Output Block Diagram
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
  - FIGURE 21-4: Comparator Analog Input Model
  - TABLE 21-1: Registers Associated with Comparator Module
22.0 Comparator Voltage Reference Module
- 22.1 Configuring the Comparator Voltage Reference
  - Register 22-1: CVRCON: Comparator Voltage Reference Control Register
  - FIGURE 22-1: Comparator Voltage Reference Block Diagram
- 22.2 Voltage Reference Accuracy/Error
- 22.3 Operation During Sleep
- 22.4 Effects of a Reset
- 22.5 Connection Considerations
  - FIGURE 22-2: Comparator Voltage Reference Output Buffer Example
  - TABLE 22-1: Registers Associated with Comparator Voltage Reference
23.0 Special Features of the CPU
- 23.1 Configuration Bits
  - 23.1.1 Considerations for Configuring the PIC18F85J90 family Devices
- 23.2 Watchdog Timer (WDT)
  - 23.2.1 Control Register
- 23.3 On-Chip Voltage Regulator
- 23.4 Two-Speed Start-up
  - FIGURE 23-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)
  - 23.4.1 Special Considerations for Using Two-Speed Start-up
- 23.5 Fail-Safe Clock Monitor
- 23.6 Program Verification and Code Protection
  - 23.6.1 Configuration Register Protection
- 23.7 In-Circuit Serial Programming
- 23.8 In-Circuit Debugger
  - TABLE 23-4: Debugger Resources
24.0 Instruction Set Summary
- 24.1 Standard Instruction Set
- 24.2 Extended Instruction Set
25.0 Development Support
- 25.1 MPLAB Integrated Development Environment Software
- 25.2 MPLAB C Compilers for Various Device Families
- 25.3 HI-TECH C for Various Device Families
- 25.4 MPASM Assembler
- 25.5 MPLINK Object Linker/ MPLIB Object Librarian
- 25.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 25.7 MPLAB SIM Software Simulator
- 25.8 MPLAB REAL ICE In-Circuit Emulator System
- 25.9 MPLAB ICD 3 In-Circuit Debugger System
- 25.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 25.12 MPLAB PM3 Device Programmer
- 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
26.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
  - FIGURE 26-1: PIC18F85J90 family Voltage-frequency Graph, Regulator Enabled (Industrial)(1)
  - FIGURE 26-2: PIC18F85J90 family Voltage-frequency Graph, Regulator Disabled (Industrial)(1,2)
- 26.1 DC Characteristics: Supply Voltage PIC18F85J90 Family (Industrial)
- 26.2 DC Characteristics: Power-Down and Supply Current PIC18F85J90 Family (Industrial)
- 26.3 DC Characteristics: PIC18F84J90 Family (Industrial)
- 26.4 AC (Timing) Characteristics
27.0 Packaging Information
- 27.1 Package Marking Information
- 27.2 Package Details
Appendix A: Revision History
- Revision A (July 2006)
- Revision B (March 2007)
- Revision C (January 2010)
Appendix B: Migration Between High-End Device Families
- TABLE B-1: Notable Differences Between PIC18F8490 and PIC18F85J90 Families
- TABLE B-2: Assignments of Moved LCD Segments
Index
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 2010 Microchip Technology Inc. DS39770C-page 219

PIC18F85J90 FAMILY

17.4.6 MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSP module is disabled. Control

of the I

C bus may be taken when the P bit is set, or the

bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user code

conducts all I

C bus operations based on Start and

Stop bit conditions.

Once Master mode is enabled, the user has six

options.

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I

C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and SCL.

The following events will cause the MSSP Interrupt

Flag bit, SSPIF, to be set (and MSSP interrupt, if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 17-18: MSSP BLOCK DIAGRAM (I

C™ MASTER MODE)

Note: The MSSP module, when configured in

C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start con-

dition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Read Write

SSPSR

Start bit, Stop bit,

SSPBUF

Internal

Data Bus

Set/Reset S, P, WCOL (SSPSTAT, SSPCON1)

Shift

Clock

MSb

LSb

SDA

Acknowledge

Generate

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

End of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

Receive Enable

Clock Cntl

Clock Arbitrate/WCOL Detect

(hold off clock source)

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM<3:0>

Start bit Detect