Datasheet
Table Of Contents
- Low-Power Features:
- LCD Driver Module Features:
- Special Microcontroller Features:
- Flexible Oscillator Structure:
- Peripheral Highlights:
- Pin Diagrams
- Pin Diagrams (Continued)
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 1.1 Core Features
- 1.2 LCD Driver
- 1.3 Other Special Features
- 1.4 Details on Individual Family Members
- TABLE 1-1: Device Features for the PIC18F85J90 family (64-pin Devices)
- TABLE 1-2: Device Features for the PIC18F85J90 family (80-pin Devices)
- FIGURE 1-1: PIC18F6XJ90 (64-pin) Block Diagram
- FIGURE 1-2: PIC18F8XJ90 (80-pin) Block Diagram
- TABLE 1-3: PIC18F6XJ90 Pinout I/O Descriptions
- TABLE 1-4: PIC18F8XJ90 Pinout I/O Descriptions
- 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers
- 3.0 Oscillator Configurations
- 3.1 Oscillator Types
- 3.2 Control Registers
- 3.3 Clock Sources and Oscillator Switching
- 3.4 External Oscillator Modes
- 3.5 Internal Oscillator Block
- 3.6 Effects of Power-Managed Modes on the Various Clock Sources
- 3.7 Power-up Delays
- 4.0 Power-Managed Modes
- 5.0 Reset
- 6.0 Memory Organization
- 6.1 Program Memory Organization
- 6.2 PIC18 Instruction Cycle
- 6.3 Data Memory Organization
- 6.4 Data Addressing Modes
- 6.5 Program Memory and the Extended Instruction Set
- 6.6 Data Memory and the Extended Instruction Set
- 7.0 Flash Program Memory
- 7.1 Table Reads and Table Writes
- 7.2 Control Registers
- 7.3 Reading the Flash Program Memory
- 7.4 Erasing Flash Program Memory
- 7.5 Writing to Flash Program Memory
- 7.6 Flash Program Operation During Code Protection
- 8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
- 8.2 Operation
- EXAMPLE 8-1: 8 x 8 Unsigned Multiply Routine
- EXAMPLE 8-2: 8 x 8 Signed Multiply Routine
- TABLE 8-1: Performance Comparison for Various Multiply Operations
- EQUATION 8-1: 16 x 16 Unsigned Multiplication Algorithm
- EXAMPLE 8-3: 16 x 16 Unsigned Multiply Routine
- EQUATION 8-2: 16 x 16 Signed Multiplication Algorithm
- EXAMPLE 8-4: 16 x 16 Signed Multiply Routine
- 9.0 Interrupts
- 10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 I/O Port Pin Capabilities
- 10.2 PORTA, TRISA and LATA Registers
- 10.3 PORTB, TRISB and LATB Registers
- 10.4 PORTC, TRISC and LATC Registers
- 10.5 PORTD, TRISD and LATD Registers
- 10.6 PORTE, TRISE and LATE Registers
- 10.7 PORTF, LATF and TRISF Registers
- 10.8 PORTG, TRISG and LATG Registers
- 10.9 PORTH, LATH and TRISH Registers
- 10.10 PORTJ, TRISJ and LATJ Registers
- 11.0 Timer0 Module
- 12.0 Timer1 Module
- 13.0 Timer2 Module
- 14.0 Timer3 Module
- 15.0 Capture/Compare/PWM (CCP) Modules
- 16.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 16-1: LCD Driver Module Block Diagram
- 16.1 LCD Registers
- 16.2 LCD Clock Source
- 16.3 LCD Bias Generation
- 16.4 LCD Multiplex Types
- 16.5 Segment Enables
- 16.6 Pixel Control
- 16.7 LCD Frame Frequency
- 16.8 LCD Waveform Generation
- FIGURE 16-6: Type-A/Type-B Waveforms in Static Drive
- FIGURE 16-7: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 16-8: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 16-9: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 16-10: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 16-11: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 16-12: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 16-13: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 16-14: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 16-15: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive
- FIGURE 16-16: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive
- 16.9 LCD Interrupts
- 16.10 Operation During Sleep
- 16.11 Configuring the LCD Module
- 17.0 Master Synchronous Serial Port (MSSP) Module
- 17.1 Master SSP (MSSP) Module Overview
- 17.2 Control Registers
- 17.3 SPI Mode
- FIGURE 17-1: MSSP Block Diagram (SPI Mode)
- 17.3.1 Registers
- 17.3.2 Operation
- 17.3.3 Enabling SPI I/O
- 17.3.4 Open-Drain Output Option
- 17.3.5 Typical Connection
- 17.3.6 Master Mode
- 17.3.7 Slave Mode
- 17.3.8 Slave Select Synchronization
- 17.3.9 Operation in Power-Managed Modes
- 17.3.10 Effects of a Reset
- 17.3.11 Bus Mode Compatibility
- 17.4 I2C Mode
- FIGURE 17-7: MSSP Block Diagram (I2C™ Mode)
- 17.4.1 Registers
- 17.4.2 Operation
- 17.4.3 Slave Mode
- EXAMPLE 17-2: Address Masking Examples
- FIGURE 17-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Address)
- FIGURE 17-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Address)
- FIGURE 17-10: I2C™ Slave Mode Timing (Transmission, 7-bit Address)
- FIGURE 17-11: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Address)
- FIGURE 17-12: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Address)
- FIGURE 17-13: I2C™ Slave Mode Timing (Transmission, 10-bit Address)
- 17.4.4 Clock Stretching
- 17.4.5 General Call Address Support
- 17.4.6 Master Mode
- 17.4.7 Baud Rate
- 17.4.8 I2C Master Mode Start Condition Timing
- 17.4.9 I2C Master Mode Repeated Start Condition Timing
- 17.4.10 I2C Master Mode Transmission
- 17.4.11 I2C Master Mode Reception
- 17.4.12 Acknowledge Sequence Timing
- 17.4.13 Stop Condition Timing
- 17.4.14 Sleep Operation
- 17.4.15 Effects of a Reset
- 17.4.16 Multi-Master Mode
- 17.4.17 Multi -Master Communication, Bus Collision and Bus Arbitration
- FIGURE 17-27: Bus Collision Timing for Transmit and Acknowledge
- FIGURE 17-28: Bus Collision During Start Condition (SDA Only)
- FIGURE 17-29: Bus Collision During Start Condition (SCL = 0)
- FIGURE 17-30: BRG Reset Due to SDA Arbitration During Start Condition
- FIGURE 17-31: Bus Collision During a Repeated Start Condition (Case 1)
- FIGURE 17-32: Bus Collision During Repeated Start Condition (Case 2)
- FIGURE 17-33: Bus Collision During a Stop Condition (Case 1)
- FIGURE 17-34: Bus Collision During a Stop Condition (Case 2)
- TABLE 17-4: Registers Associated with I2C™ Operation
- 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 18.1 Control Registers
- 18.2 EUSART Baud Rate Generator (BRG)
- 18.3 EUSART Asynchronous Mode
- 18.4 EUSART Synchronous Master Mode
- 18.5 EUSART Synchronous Slave Mode
- 19.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART)
- 19.1 Control Registers
- 19.2 AUSART Baud Rate Generator (BRG)
- 19.3 AUSART Asynchronous Mode
- 19.4 AUSART Synchronous Master Mode
- 19.5 AUSART Synchronous Slave Mode
- 20.0 10-bit Analog-to-Digital Converter (A/D) Module
- Register 20-1: ADCON0: A/D Control Register 0
- Register 20-2: ADCON1: A/D Control Register 1
- Register 20-3: ADCON2: A/D Control Register 2
- FIGURE 20-1: A/D Block Diagram(1,2)
- FIGURE 20-2: Analog Input Model
- 20.1 A/D Acquisition Requirements
- 20.2 Selecting and Configuring Automatic Acquisition Time
- 20.3 Selecting the A/D Conversion Clock
- 20.4 Configuring Analog Port Pins
- 20.5 A/D Conversions
- 20.6 Use of the CCP2 Trigger
- 20.7 A/D Converter Calibration
- 20.8 Operation in Power-Managed Modes
- 21.0 Comparator Module
- Register 21-1: CMCON: Comparator Module Control Register
- 21.1 Comparator Configuration
- 21.2 Comparator Operation
- 21.3 Comparator Reference
- 21.4 Comparator Response Time
- 21.5 Comparator Outputs
- 21.6 Comparator Interrupts
- 21.7 Comparator Operation During Sleep
- 21.8 Effects of a Reset
- 21.9 Analog Input Connection Considerations
- 22.0 Comparator Voltage Reference Module
- 23.0 Special Features of the CPU
- 23.1 Configuration Bits
- 23.1.1 Considerations for Configuring the PIC18F85J90 family Devices
- TABLE 23-1: Mapping of the Flash Configuration Words to the Configuration Registers
- TABLE 23-2: Configuration Bits and Device IDs
- Register 23-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)
- Register 23-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 23-3: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 23-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
- Register 23-5: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
- Register 23-6: DEVID1: Device ID Register 1 for PIC18F85J90 family Devices
- Register 23-7: DEVID2: Device ID Register 2 for PIC18F85J90 family Devices
- 23.1.1 Considerations for Configuring the PIC18F85J90 family Devices
- 23.2 Watchdog Timer (WDT)
- 23.3 On-Chip Voltage Regulator
- 23.4 Two-Speed Start-up
- 23.5 Fail-Safe Clock Monitor
- 23.6 Program Verification and Code Protection
- 23.7 In-Circuit Serial Programming
- 23.8 In-Circuit Debugger
- 23.1 Configuration Bits
- 24.0 Instruction Set Summary
- 24.1 Standard Instruction Set
- 24.2 Extended Instruction Set
- 25.0 Development Support
- 25.1 MPLAB Integrated Development Environment Software
- 25.2 MPLAB C Compilers for Various Device Families
- 25.3 HI-TECH C for Various Device Families
- 25.4 MPASM Assembler
- 25.5 MPLINK Object Linker/ MPLIB Object Librarian
- 25.6 MPLAB Assembler, Linker and Librarian for Various Device Families
- 25.7 MPLAB SIM Software Simulator
- 25.8 MPLAB REAL ICE In-Circuit Emulator System
- 25.9 MPLAB ICD 3 In-Circuit Debugger System
- 25.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express
- 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express
- 25.12 MPLAB PM3 Device Programmer
- 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
- 26.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 26.1 DC Characteristics: Supply Voltage PIC18F85J90 Family (Industrial)
- 26.2 DC Characteristics: Power-Down and Supply Current PIC18F85J90 Family (Industrial)
- 26.3 DC Characteristics: PIC18F84J90 Family (Industrial)
- 26.4 AC (Timing) Characteristics
- 26.4.1 Timing Parameter Symbology
- 26.4.2 Timing Conditions
- 26.4.3 Timing Diagrams and Specifications
- FIGURE 26-4: External Clock Timing
- TABLE 26-7: External Clock Timing Requirements
- TABLE 26-8: PLL Clock Timing Specifications (Vdd = 2.15V to 3.6V)
- TABLE 26-9: Internal RC Accuracy (INTOSC and INTRC Sources)
- FIGURE 26-5: CLKO and I/O Timing
- TABLE 26-10: CLKO and I/O Timing Requirements
- FIGURE 26-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- TABLE 26-11: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements
- FIGURE 26-7: Timer0 and Timer1 External Clock Timings
- TABLE 26-12: Timer0 and Timer1 External Clock Requirements
- FIGURE 26-8: Capture/Compare/PWM Timings (CCP1, CCP2 Modules)
- TABLE 26-13: Capture/Compare/PWM Requirements (CCP1, CCP2 Modules)
- FIGURE 26-9: Example SPI Master Mode Timing (CKE = 0)
- TABLE 26-14: Example SPI Mode Requirements (Master Mode, Cke = 0)
- FIGURE 26-10: Example SPI Master Mode Timing (CKE = 1)
- TABLE 26-15: Example SPI Mode Requirements (Master Mode, CKE = 1)
- FIGURE 26-11: Example SPI Slave Mode Timing (CKE = 0)
- TABLE 26-16: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)
- FIGURE 26-12: Example SPI Slave Mode Timing (CKE = 1)
- TABLE 26-17: Example SPI Slave Mode Requirements (CKE = 1)
- FIGURE 26-13: I2C™ Bus Start/Stop Bits Timing
- TABLE 26-18: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)
- FIGURE 26-14: I2C™ Bus Data Timing
- TABLE 26-19: I2C™ Bus Data Requirements (Slave Mode)
- FIGURE 26-15: MSSP I2C™ Bus Start/Stop Bits Timing Waveforms
- TABLE 26-20: MSSP I2C™ Bus Start/Stop Bits Requirements
- FIGURE 26-16: MSSP I2C™ Bus Data Timing
- TABLE 26-21: MSSP I2C™ Bus Data Requirements
- FIGURE 26-17: EUSART/AUSART Synchronous Transmission (Master/Slave) Timing
- TABLE 26-22: EUSART/AUSART Synchronous Transmission Requirements
- FIGURE 26-18: EUSART/AUSART Synchronous Receive (Master/Slave) Timing
- TABLE 26-23: EUSART/AUSART Synchronous Receive Requirements
- TABLE 26-24: A/D Converter Characteristics: PIC18F85J90 family (Industrial)
- FIGURE 26-19: A/D Conversion Timing
- TABLE 26-25: A/D Conversion Requirements
- 27.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Migration Between High-End Device Families
- Index
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales and Service
2010 Microchip Technology Inc. DS39770C-page 217
PIC18F85J90 FAMILY
FIGURE 17-16: I
2
C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S
123456789 123456789 12345 789
P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software
Cleared in software
SSPOV (SSPCON1<6>)
CKP written to
‘
1
’
Note: An update of the SSPADD register before the
falling edge of the ninth clock will have no effect
on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock
of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to
‘
1
’
Clock is not held low
because ACK =
1