Datasheet

PIC18F85J90 FAMILY
DS39770C-page 174  2010 Microchip Technology Inc.
16.7 LCD Frame Frequency
The rate at which the COM and SEG outputs changes
is called the LCD frame frequency. Frame frequency is
set by the LP<3:0> bits (LCDPS<3:0>), and is also
affected by the Multiplex mode being used. The rela-
tionship between the Multiplex mode, LP bits setting
and frame rate is shown in Table 16-4 and Table 16-5.
TABLE 16-4: FRAME FREQUENCY
FORMULAS
TABLE 16-5: APPROXIMATE FRAME
FREQUENCY (IN Hz) FOR LP
PRESCALER SETTINGS
16.8 LCD Waveform Generation
LCD waveform generation is based on the principle
that the net AC voltage across the dark pixel should be
maximized and the net AC voltage across the clear
pixel should be minimized. The net DC voltage across
any pixel should be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data. The
pixel signal (COM-SEG) will have no DC component
and it can take only one of the two rms values. The
higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In the Type-A waveform, the
phase changes within each common type, whereas in
the Type-B waveform, the phase changes on each
frame boundary. Thus, the Type-A waveform maintains
0 V
DC over a single frame, whereas the Type-B
waveform takes two frames.
Figure 16-6 through Figure 16-16 provide waveforms
for static, half multiplex, one-third multiplex and quarter
multiplex drives for Type-A and Type-B waveforms.
Multiplex
Mode
Frame Frequency (Hz)
Static Clock source/(4 x 1 x (LP3:LP0 + 1))
1/2 Clock source/(2 x 2 x (LP3:LP0 + 1))
1/3 Clock source/(1 x 3 x (LP3:LP0 + 1))
1/4 Clock source/(1 x 4 x (LP3:LP0 + 1))
LP<3:0>
Multiplex Mode
Static 1/2 1/3 1/4
1 125 125 167 125
2 83 83 111 83
3 62628362
4 50506750
5 42425642
6 36364836
7 31314231
Note 1: If the power-managed Sleep mode is
invoked while the LCD Sleep bit is set
(LCDCON<6> is ‘1’), take care to execute
Sleep only when the V
DC on all the pixels
is ‘0’.
2: When the LCD clock source is the system
clock, the LCD module will go to Sleep if
the microcontroller goes into Sleep mode,
regardless of the setting of the SPLEN bit.
Thus, always take care to see that the V
DC
on all pixels is ‘0’ whenever Sleep mode is
invoked.