Datasheet

PIC18F85J90 FAMILY
DS39770C-page 170  2010 Microchip Technology Inc.
16.3.3 BIAS CONFIGURATIONS
PIC18F85J90 family devices have four distinct circuit
configurations for LCD bias generation:
• M0: Regulator with Boost
• M1: Regulator without Boost
• M2: Resistor Ladder with Software Contrast
• M3: Resistor Ladder with Hardware Contrast
16.3.3.1 M0 (Regulator with Boost)
In M0 operation, the LCD charge pump feature is
enabled. This allows the regulator to generate voltages
up to +3.6V to the LCD (as measured at LCDBIAS3).
M0 uses a flyback capacitor connected between
V
LCAP1 and VLCAP2, as well as filter capacitors on
LCDBIAS0 through LCDBIAS3, to obtain the required
voltage boost (Figure 16-3).
The output voltage (V
BIAS) is the difference of potential
between LCDBIAS3 and LCDBIAS0. It is set by the
BIAS<2:0> bits which adjust the offset between
LCDBIAS0 and V
SS. The flyback capacitor (CFLY) acts
as a charge storage element for large LCD loads. This
mode is useful in those cases where the voltage
requirements of the LCD are higher than the micro-
controller’s V
DD. It also permits software control of the
display’s contrast by adjustment of bias voltage by
changing the value of the BIAS bits.
M0 supports Static and 1/3 Bias types. Generation of
the voltage levels for 1/3 Bias is handled automatically,
but must be configured in software.
M0 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
setting the CPEN bit. If static Bias type is required, the
MODE13 bit must be cleared.
16.3.3.2 M1 (Regulator without Boost)
M1 operation is similar to M0, but does not use the LCD
charge pump. It can provide V
BIAS up to the voltage
level supplied directly to LCDBIAS3. It can be used in
cases where VDD for the application is expected to
never drop below a level that can provide adequate
contrast for the LCD. The connection of external com-
ponents is very similar to M0, except that LCDBIAS3
must be tied directly to V
DD (Figure 16-3).
The BIAS<2:0> bits can still be used to adjust contrast
in software by changing V
BIAS. As with M0, changing
these bits changes the offset between LCDBIAS0 and
VSS. In M1, this is reflected in the change between the
LCDBIAS0 and the voltage tied to LCDBIAS3. Thus, if
VDD should change, VBIAS will also change; where in
M0, the level of V
BIAS is constant.
Like M0, M1 supports Static and 1/3 Bias types.
Generation of the voltage levels for 1/3 Bias is handled
automatically but must be configured in software.
M1 is enabled by selecting a valid regulator clock
source (CKSEL<1:0> set to any value except ‘00’) and
clearing the CPEN bit. If 1/3 Bias type is required, the
MODE13 bit should also be set.
FIGURE 16-3: LCD REGULATOR CONNECTIONS FOR M0 AND M1 CONFIGURATIONS
Note: When the device is put to Sleep while
operating in M0 or M1 mode, make sure
that the Bias capacitors are fully discharged
to get the lowest Sleep current.
LCDBIAS3
LCDBIAS2
LCDBIAS1
LCDBIAS0
AV
DD
PIC18F85J90
VDD
VLCAP1
V
LCAP2
CFLY
C0
C1
C2
C3
C0
C1
C2
VDD
VDD
(VBIAS up to 3.6V)
Mode 0
(VBIAS  VDD)
Mode 1
CFLY
Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer
based on the actual LCD specifications.
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)
0.047 F
(1)