Datasheet

 2010 Microchip Technology Inc. DS39770C-page 115
PIC18F85J90 FAMILY
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Data Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the Data Latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding port
pin an input (i.e., puts the corresponding output driver
in a High-Impedance mode). Clearing a TRIS bit (= 0)
makes the corresponding port pin an output (i.e., puts
the contents of the corresponding LAT bit on the
selected pin).
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
the PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
DD input levels.
10.1.1 INPUT PINS AND VOLTAGE
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Most pins that
are used as digital only inputs are able to handle DC
volta ges up to 5.5V, a level typical for digital logic
circuits. The digital pins that cannot exceed V
DD are
RE0, RE1, RE2, RG0, RG2 and RG3.
In contrast, pins that also have analog input functions of
any kind can only tolerate voltages up to V
DD. Voltage
excursions beyond V
DD on these pins should be avoided.
Table 10-1 summarizes the input voltage capabilities.
Refer to Section 26.0 “Electrical Characteristics” for
more details.
TABLE 10-1: INPUT VOLTAGE TOLERANCE
10.1.2 PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
PORTB and PORTC, as well as PORTA<7:6>, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ can also drive LEDs but
only those with smaller current requirements. PORTF,
PORTG and PORTH, along with PORTA<5:0>, have
the lowest drive level but are capable of driving normal
digital circuit loads with a high input impedance.
Regardless of which port it is located on, all output pins
in LCD Segment or Common mode have sufficient
output to directly drive a display.
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 26.0 “Electrical Characteristics” for more
details.
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin
(1)
QD
CKx
QD
CKx
EN
QD
EN
RD LAT
or PORT
Note 1: I/O pins have diode protection to V
DD and VSS.
PORT or Pin
Tolerated
Input
Description
PORTA<7:0> V
DD Only VDD input levels
are tolerated.
PORTC<1:0>
PORTF<7:1>
PORTB<7:0> 5.5V Tolerates input levels
above VDD; useful for
most standard logic.
PORTC<7:2>
PORTD<7:0>
PORTE<7:3>
PORTG<4,1>
PORTH<7:0>
(1)
PORTJ<7:0>
(1)
Note 1: Not available on 64-pin devices.