PIC18F85J90 Family Data Sheet 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F85J90 FAMILY 64/80-Pin, High-Performance Microcontrollers with LCD Driver and nanoWatt Technology Low-Power Features: Flexible Oscillator Structure: • • • • • • • Two Crystal modes, 4-25 MHz • Two External Clock modes, up to 40 MHz • Internal Oscillator Block: - 8 user-selectable frequencies from 31.
PIC18F85J90 FAMILY Pin Diagrams 64-Pin TQFP RD7/SEG7 RD6/SEG6 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 VSS VDD RD0/SEG0 RE7/CCP2(1)/SEG31 RE6/COM3 RE5/COM2 RE4/COM1 RE3/COM0 LCDBIAS3 Pins are up to 5.
PIC18F85J90 FAMILY Pin Diagrams (Continued) 80-Pin TQFP RJ1/SEG33 RJ0 RD7/SEG7 RD6/SEG6 RD5/SEG5 RD4/SEG4 RD3/SEG3 RD2/SEG2 RD1/SEG1 VDD VSS RE7/CCP2(1)/SEG31 RD0/SEG0 RE6/COM3 RE5/COM2 RE4/COM1 RE3/COM0 LCDBIAS3 RH0/SEG47 RH1/SEG46 Pins are up to 5.
PIC18F85J90 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31 3.0 Oscillator Configurations ....................................................................................
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PIC18F85J90 FAMILY NOTES: DS39770C-page 8 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F63J90 • PIC18F64J90 • PIC18F65J90 • PIC18F83J90 • PIC18F84J90 • PIC18F85J90 This family combines the traditional advantages of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – with a versatile on-chip LCD driver, while maintaining an extremely competitive price point.
PIC18F85J90 FAMILY 1.2 LCD Driver 1.4 Details on Individual Family Members The on-chip LCD driver includes many features that make the integration of displays in low-power applications easier. These include an integrated voltage regulator with charge pump that allows contrast control in software and display operation above device VDD. Devices in the PIC18F85J90 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. 1.3 1.
PIC18F85J90 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F85J90 FAMILY (64-PIN DEVICES) Features PIC18F63J90 Operating Frequency Program Memory (Bytes) PIC18F64J90 PIC18F65J90 DC – 40 MHz 8K 16K 32K Program Memory (Instructions) 4096 8192 16384 Data Memory (Bytes) 1024 1024 2048 Interrupt Sources 27 I/O Ports Ports A, B, C, D, E, F, G LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs) Timers 4 Capture/Compare/PWM Modules 2 Serial Communications MSSP, Addressable USAR
PIC18F85J90 FAMILY FIGURE 1-1: PIC18F6XJ90 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch Program Memory (96 Kbytes) STKPTR 12 PORTC RC0:RC7(1) inc/dec logic Table Latch Instruction Bus <16> PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 RA0:RA7(1,2) Data Memory (2.0, 3.
PIC18F85J90 FAMILY FIGURE 1-2: PIC18F8XJ90 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 31 Level Stack 4 BSR STKPTR PORTC RC0:RC7(1) 12 inc/dec logic Table Latch Instruction Bus <16> RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 PORTB 12 Data Address<12> Address Latch Program Memory (96 Kbytes) RA0:RA7(1,2) Data Memory (2.0, 3.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS Pin Name Pin Number TQFP MCLR 7 OSC1/CLKI/RA7 OSC1 CLKI 39 Pin Buffer Type Type I ST I I CMOS CMOS I/O TTL O — CLKO O — RA6 I/O TTL RA7 OSC2/CLKO/RA6 OSC2 40 Description Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input. External clock source input. Always associated with pin function OSC1.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0 RD0 SEG0 58 RD1/SEG1 RD1 SEG1 55 RD2/SEG2 RD2 SEG2 54 RD3/SEG3 RD3 SEG3 53 RD4/SEG4 RD4 SEG4 52 RD5/SEG5 RD5 SEG5 51 RD6/SEG6 RD6 SEG6 50 RD7/SEG7 RD7 SEG7 49 I/O O ST Analog Digital I/O. SEG0 output for LCD. I/O O ST Analog Digital I/O. SEG1 output for LCD. I/O O ST Analog Digital I/O.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. RE0/LCDBIAS1 RE0 LCDBIAS1 2 RE1/LCDBIAS2 RE1 LCDBIAS2 1 LCDBIAS3 64 RE3/COM0 RE3 COM0 63 RE4/COM1 RE4 COM1 62 RE5/COM2 RE5 COM2 61 RE6/COM3 RE6 COM3 60 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 59 I/O I ST Analog Digital I/O. BIAS1 input for LCD. I/O I ST Analog Digital I/O. BIAS2 input for LCD.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/SEG19 RF1 AN6 C2OUT SEG19 17 RF2/AN7/C1OUT/SEG20 RF2 AN7 C1OUT SEG20 16 RF3/AN8/SEG21 RF3 AN8 SEG21 15 RF4/AN9/SEG22 RF4 AN9 SEG22 14 RF5/AN10/CVREF/SEG23 RF5 AN10 CVREF SEG23 13 RF6/AN11/SEG24 RF6 AN11 SEG24 12 RF7/AN5/SS/SEG25 RF7 AN5 SS SEG25 11 I/O I O O ST Analog — Analog Digital I/O.
PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/LCDBIAS0 RG0 LCDBIAS0 3 RG1/TX2/CK2 RG1 TX2 CK2 4 RG2/RX2/DT2/VLCAP1 RG2 RX2 DT2 VLCAP1 5 RG3/VLCAP2 RG3 VLCAP2 6 RG4/SEG26 RG4 SEG26 8 I/O I ST Analog Digital I/O. BIAS0 input for LCD. I/O O I/O ST — ST Digital I/O. AUSART asynchronous transmit. AUSART synchronous clock (see related RX2/DT2).
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS Pin Name Pin Number TQFP MCLR 9 OSC1/CLKI/RA7 OSC1 CLKI 49 Pin Buffer Type Type I ST I I CMOS CMOS I/O TTL O — CLKO O — RA6 I/O TTL RA7 OSC2/CLKO/RA6 OSC2 50 Description Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input. External clock source input. Always associated with pin function OSC1.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTC is a bidirectional I/O port.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTD is a bidirectional I/O port. RD0/SEG0 RD0 SEG0 72 RD1/SEG1 RD1 SEG1 69 RD2/SEG2 RD2 SEG2 68 RD3/SEG3 RD3 SEG3 67 RD4/SEG4 RD4 SEG4 66 RD5/SEG5 RD5 SEG5 65 RD6/SEG6 RD6 SEG6 64 RD7/SEG7 RD7 SEG7 63 I/O O ST Analog Digital I/O. SEG0 output for LCD. I/O O ST Analog Digital I/O. SEG1 output for LCD. I/O O ST Analog Digital I/O.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTE is a bidirectional I/O port. RE0/LCDBIAS1 RE0 LCDBIAS1 4 RE1/LCDBIAS2 RE1 LCDBIAS2 3 LCDBIAS3 78 RE3/COM0 RE3 COM0 77 RE4/COM1 RE4 COM1 76 RE5/COM2 RE5 COM2 75 RE6/COM3 RE6 COM3 74 RE7/CCP2/SEG31 RE7 CCP2(2) SEG31 73 I/O I ST Analog Digital I/O. BIAS1 input for LCD. I/O I ST Analog Digital I/O. BIAS2 input for LCD.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT/SEG19 RF1 AN6 C2OUT SEG19 23 RF2/AN7/C1OUT/SEG20 RF2 AN7 C1OUT SEG20 18 RF3/AN8/SEG21 RF3 AN8 SEG21 17 RF4/AN9/SEG22 RF4 AN9 SEG22 16 RF5/AN10/CVREF/SEG23 RF5 AN10 CVREF SEG23 15 RF6/AN11/SEG24 RF6 AN11 SEG24 14 RF7/AN5/SS/SEG25 RF7 AN5 SS SEG25 13 I/O I O O ST Analog — Analog Digital I/O.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTG is a bidirectional I/O port. RG0/LCDBIAS0 RG0 LCDBIAS0 5 RG1/TX2/CK2 RG1 TX2 CK2 6 RG2/RX2/DT2/VLCAP1 RG2 RX2 DT2 VLCAP1 7 RG3/VLCAP2 RG3 VLCAP2 8 RG4/SEG26 RG4 SEG26 10 I/O I ST Analog Digital I/O. BIAS0 input for LCD. I/O O I/O ST — ST Digital I/O. AUSART asynchronous transmit. AUSART synchronous clock (see related RX2/DT2).
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTH is a bidirectional I/O port. RH0/SEG47 RH0 SEG47 79 RH1/SEG46 RH1 SEG46 80 RH2/SEG45 RH2 SEG45 1 RH3/SEG44 RH3 SEG44 2 RH4/SEG40 RH4 SEG40 22 RH5/SEG41 RH5 SEG41 21 RH6/SEG42 RH6 SEG42 20 RH7/SEG43 RH7 SEG43 19 I/O O ST Analog Digital I/O. SEG47 output for LCD. I/O O ST Analog Digital I/O. SEG46 output for LCD.
PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number TQFP Pin Buffer Type Type Description PORTJ is a bidirectional I/O port. RJ0 62 RJ1/SEG33 RJ1 SEG33 61 RJ2/SEG34 RJ2 SEG34 60 RJ3/SEG35 RJ3 SEG35 59 RJ4/SEG39 RJ4 SEG39 39 RJ5/SEG38 RJ5 SEG38 40 RJ6/SEG37 RJ6 SEG37 41 RJ7/SEG36 RJ7 SEG36 42 I/O ST Digital I/O. I/O O ST Analog Digital I/O. SEG33 output for LCD. I/O O ST Analog Digital I/O. SEG34 output for LCD.
PIC18F85J90 FAMILY NOTES: DS39770C-page 30 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.
PIC18F85J90 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F85J90 FAMILY 2.4 Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. Refer to Section 23.3 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator.
PIC18F85J90 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F85J90 FAMILY 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types Five of these are selected by the user by programming the FOSC<2:0> Configuration bits. The sixth mode (INTRC) may be invoked under software control; it can also be configured as the default mode on device Resets. The PIC18F85J90 family of devices can be operated in six different oscillator modes: 1. 2. 3. 4. 5. 6.
PIC18F85J90 FAMILY 3.2 Control Registers The OSCTUNE register (Register 3-2) controls the tuning and operation of the internal oscillator block. It also implements the PLLEN bits, which control the operation of the Phase Locked Loop (PLL) in Internal Oscillator modes (see Section 3.4.3 “PLL Frequency Multiplier”). The OSCCON register (Register 3-1) controls the main aspects of the device clock’s operation.
PIC18F85J90 FAMILY REGISTER 3-2: R/W-0 INTSRC OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 PLLEN (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F85J90 FAMILY 3.3.1 CLOCK SOURCE SELECTION The System Clock Select bits, SCS<1:0> (OSCCON<1:0>), select the clock source. The available clock sources are the primary clock defined by the FOSC<1:0> Configuration bits, the secondary clock (Timer1 oscillator) and the internal oscillator. The clock source changes after one or more of the bits are written to, following a brief clock transition interval.
PIC18F85J90 FAMILY 3.4 External Oscillator Modes 3.4.1 TABLE 3-2: CRYSTAL OSCILLATOR/CERAMIC RESONATORS (HS MODES) In HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-2 shows the pin connections. The oscillator design requires the use of a parallel resonant crystal. Note: Use of a series resonant crystal may give a frequency out of the crystal manufacturer’s specifications.
PIC18F85J90 FAMILY EXTERNAL CLOCK INPUT (EC MODES) The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-3 shows the pin connections for the EC Oscillator mode.
PIC18F85J90 FAMILY 3.5 Internal Oscillator Block The PIC18F85J90 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. The main output is the Fast RC oscillator, or INTOSC, an 8 MHz clock source which can be used to directly drive the device clock.
PIC18F85J90 FAMILY 3.6 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F85J90 FAMILY 4.0 POWER-MANAGED MODES 4.1.1 CLOCK SOURCES The PIC18F85J90 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power.
PIC18F85J90 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set while in a given power-managed mode.
PIC18F85J90 FAMILY Note: On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
PIC18F85J90 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18F85J90 FAMILY 4.3 Sleep Mode 4.4 The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate.
PIC18F85J90 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F85J90 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP.
PIC18F85J90 FAMILY NOTES: DS39770C-page 50 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 5.0 RESET 5.1 The PIC18F85J90 family of devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset RCON Register Device Reset events are tracked through the RCON register (Register 5-1).
PIC18F85J90 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0
PIC18F85J90 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. 5.3 D C Power-on Reset events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs; it does not change for any other Reset event.
PIC18F85J90 FAMILY A CM Reset behaves similarly to a Master Clear Reset, RESET instruction, WDT time-out or Stack Event Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. 5.6 Power-up Timer (PWRT) PIC18F85J90 family devices incorporate an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled.
PIC18F85J90 FAMILY FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 5.7 Reset State of Registers Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred.
PIC18F85J90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets TOSU PIC18F6XJ90 PIC18F8XJ90 ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XJ90 PIC18F8XJ90 uu-0 0000 00-0 0000 uu-u uuuu(1) PCLATU PIC18F6XJ90 PIC18F8XJ90 ---0 0000 ---0
PIC18F85J90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets FSR1H PIC18F6XJ90 PIC18F8XJ90 ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6XJ90 PIC18F8XJ90 ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A POSTINC2 PIC18F6XJ90 PIC18F8XJ90 N/A N/A N/A Register Wake-up
PIC18F85J90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6XJ90 PIC18F8XJ90 0-00 0000 0-00 0000 u-uu uuuu ADCON1 PIC18F6XJ90 PIC18F8XJ90 --00 0000 --00 0000 --uu uuuu ADCON2 PIC18F6XJ90 PIC18F8XJ90 0-00 0000 0-00 00
PIC18F85J90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt IPR3 PIC18F6XJ90 PIC18F8XJ90 -111 -11- -111 -11- -uuu -uu- PIR3 PIC18F6XJ90 PIC18F8XJ90 -000 -00- -000 -00- -uuu -00-(3) PIE3 PIC18F6XJ90 PIC18F8XJ90 -000 -00- -000 -00- -uuu -00- IPR2 PIC18F6XJ90 PIC18F8XJ90 11-- 111- 11-- 111- uu-- uuu- PIR2 PI
PIC18F85J90 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt PORTE PIC18F6XJ90 PIC18F8XJ90 xxxx x-xx uuuu u-uu uuuu u-uu PORTD PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu PORTA(5
PIC18F85J90 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets CCPR2L PIC18F6XJ90 PIC18F8XJ90 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6XJ90 PIC18F8XJ90 --00 0000 --00 0000 --uu uuuu SPBRG2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6XJ90 PIC18F8XJ90 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6XJ90 PIC18F8XJ90 0000 0000
PIC18F85J90 FAMILY 6.0 MEMORY ORGANIZATION There are two types of memory in PIC18 Flash microcontroller devices: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 “Flash Program Memory”. FIGURE 6-1: 6.
PIC18F85J90 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. Because PIC18F85J90 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information.
PIC18F85J90 FAMILY 6.1.3 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F85J90 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value.
PIC18F85J90 FAMILY 6.1.4.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 1L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
PIC18F85J90 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 6.2.2 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F85J90 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 6.1.3 “Program Counter”).
PIC18F85J90 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F85J90 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18FX3J90/X4J90 DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h GPR FFh 00h = 0100 000h 05Fh 060h 0FFh 100h The BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15).
PIC18F85J90 FAMILY FIGURE 6-7: DATA MEMORY MAP FOR PIC18FX5J90 DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h GPR FFh 00h Bank 4 = 1111 DS39770C-page 72 The second 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction.
PIC18F85J90 FAMILY FIGURE 6-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 11 1 11 1 0 11 11 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F85J90 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 6-2 and Table 6-3.
PIC18F85J90 FAMILY TABLE 6-3: File Name PIC18F85J90 FAMILY REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page ---0 0000 57, 65 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 57, 65 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 57, 65 Return Stack Pointer uu-0 0000 57, 66 Holding Register for PC<20:16> TOSU STKPTR STKFUL STKUNF — PCLATU — — bit 21(1) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0 0000 57, 65 PC
PIC18F85J90 FAMILY TABLE 6-3: File Name PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page TMR0H Timer0 Register High Byte 0000 0000 58, 139 TMR0L Timer0 Register Low Byte xxxx xxxx 58, 139 58, 137 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 OSCCON T0CON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 36, 58 LCDREG — CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0
PIC18F85J90 FAMILY TABLE 6-3: File Name PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page SPBRG1 EUSART Baud Rate Generator 0000 0000 59, 240 RCREG1 EUSART Receive Register 0000 0000 59, 248 TXREG1 EUSART Transmit Register 0000 0000 59, 246 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 59, 236 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 59, 237 LCDPS WFT
PIC18F85J90 FAMILY TABLE 6-3: File Name PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page 60, 136 PORTJ(2) RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx xxxx 60, 134 RDPU REPU RJPU(2) RG4 RG3 RG2 RG1 RG0 000x xxxx 60, 132 60, 130 PORTG PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 — xxxx xxx- PORTE RE7 RE6 RE5 RE4 RE3 — RE1 RE0 xxxx x
PIC18F85J90 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F85J90 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F85J90 FAMILY 6.4.3.1 FSR Registers and the INDF Operand the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F85J90 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F85J90 FAMILY 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands.
PIC18F85J90 FAMILY FIGURE 6-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
PIC18F85J90 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F85J90 FAMILY NOTES: DS39770C-page 86 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
PIC18F85J90 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 7.2 The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”.
PIC18F85J90 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — — FREE WRERR WREN WR — bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit (cannot be cleared in software) -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the n
PIC18F85J90 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F85J90 FAMILY 7.3 Reading the Flash Program Memory The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The TBLPTR points to a byte address in program space.
PIC18F85J90 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR<21:10> point to the block being erased; TBLPTR<9:0> are ignored.
PIC18F85J90 FAMILY 7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming.
PIC18F85J90 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base address ; of the memory block, minus 1 BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D
PIC18F85J90 FAMILY 7.5.2 7.6 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.3 Flash Program Operation During Code Protection See Section 23.6 “Program Verification and Code Protection” for details on code protection of Flash program memory.
PIC18F85J90 FAMILY NOTES: DS39770C-page 96 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction EXAMPLE 8-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the Product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 8-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18F85J90 FAMILY Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F85J90 FAMILY 9.0 INTERRUPTS Members of the PIC18F85J90 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F85J90 FAMILY FIGURE 9-1: PIC18F85J90 FAMILY INTERRUPT LOGIC PIR1<6:3,1:0> PIE1<6:3,1:0> IPR1<6:3,1:0> PIR2<7:6,3:1> PIE2<7:6 3:1> IPR2<7:6,3:1> Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR3<6:4,2:1> PIE3<6:4,2:1> IPR3<6:4,2:1> IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<6:3,1:0> PIE
PIC18F85J90 FAMILY 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F85J90 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Int
PIC18F85J90 FAMILY REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low
PIC18F85J90 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F85J90 FAMILY REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 OSCFIF CMIF — — BCLIF LVDIF TMR3IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device c
PIC18F85J90 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 U-0 — LCDIF RC2IF TX2IF — CCP2IF CCP1IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected) 1 = LCD data of all COMs
PIC18F85J90 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F85J90 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 OSCFIE CMIE — — BCLIE LVDIE TMR3IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’
PIC18F85J90 FAMILY REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 U-0 — LCDIE RC2IE TX2IE — CCP2IE CCP1IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected) 1 = Enabled 0 = Disabled bit 5
PIC18F85J90 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F85J90 FAMILY REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 U-0 OSCFIP CMIP — — BCLIP LVDIP TMR3IP — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-4
PIC18F85J90 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 R/W-1 R-1 R-1 U-0 R/W-1 R/W-1 U-0 — LCDIP RC2IP TX2IP — CCP2IP CCP1IP — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected) 1 = High priority 0 = Low
PIC18F85J90 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F85J90 FAMILY 9.6 INTx Pin Interrupts 9.7 External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F85J90 FAMILY 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
PIC18F85J90 FAMILY TABLE 10-2: OUTPUT DRIVE LEVELS FOR VARIOUS PORTS Low Medium High PORTA<5:0> PORTD PORTA<7:6> PORTF PORTE PORTB PORTG PORTJ (1) 10.1.3 Not available on 64-pin devices. PULL-UP CONFIGURATION Four of the I/O ports (PORTB, PORTD, PORTE and PORTJ) implement configurable weak pull-ups on all pins. These are internal pull-ups that allow floating digital input signals to be pulled to a consistent level without the use of external resistors.
PIC18F85J90 FAMILY TABLE 10-3: PORTA FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RA0 0 O DIG 1 I TTL PORTA<0> data input; disabled when analog input is enabled. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input enabled. AN1 1 I ANA A/D Input Channel 1.
PIC18F85J90 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISB and LATB. All pins on PORTB are digital only and tolerate voltages up to 5.5V.
PIC18F85J90 FAMILY TABLE 10-5: Pin Name RB0/INT0/SEG30 RB1/INT1/SEG8 PORTB FUNCTIONS Function TRIS Setting I/O I/O Type RB0 0 O DIG 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. INT0 1 I ST External Interrupt 0 input. SEG30 x O ANA LCD Segment 30 output; disables all other pin functions. RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. 1 I ST External Interrupt 1 input.
PIC18F85J90 FAMILY TABLE 10-6: Name PORTB LATB TRISB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 61 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 60 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 60 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 57 INTCON3 IN
PIC18F85J90 FAMILY 10.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISC and LATC. Only PORTC pins, RC2 through RC7, are digital only pins and can tolerate input voltages up to 5.5V. PORTC is multiplexed with CCP, MSSP and EUSART peripheral functions (Table 10-7). The pins have Schmitt Trigger input buffers.
PIC18F85J90 FAMILY TABLE 10-7: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI/ CCP2/SEG32 RC2/CCP1/ SEG13 PORTC FUNCTIONS Function TRIS Setting I/O I/O Type RC0 0 O DIG LATC<0> data output. 1 I ST PORTC<0> data input. T1OSO x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST PORTC<1> data input. T1OSI x I ANA Timer1 oscillator input. CCP2(1) 0 O DIG CCP2 compare/PWM output.
PIC18F85J90 FAMILY TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 61 LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 60 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60 U1OD — Name PORTC LATG U2OD TRISG SPIOD CCP2OD CCP1OD LATG4 LATG3 LATG2 LATG1 LATG0 60 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60 LCDSE1 SE15 SE14 SE13 S
PIC18F85J90 FAMILY 10.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISD and LATD. All pins on PORTD are digital only and tolerate voltages up to 5.5V. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset. Each of the PORTD pins has a weak internal pull-up.
PIC18F85J90 FAMILY TABLE 10-9: Pin Name RD0/SEG0 RD1/SEG1 RD2/SEG2 RD3/SEG3 RD4/SEG4 RD5/SEG5 RD6/SEG6 RD7/SEG7 PORTD FUNCTIONS Function TRIS Setting I/O I/O Type RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. SEG0 x O ANA LCD Segment 0 output; disables all other pin functions. RD1 0 O DIG LATD<1> data output. 1 I ST SEG1 x O ANA LCD Segment 1 output; disables all other pin functions. RD2 0 O DIG LATD<2> data output.
PIC18F85J90 FAMILY 10.6 PORTE, TRISE and LATE Registers PORTE is a 7-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISE and LATE. All pins on PORTE are digital only and tolerate voltages up to 5.5V. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. The RE7 pin is also configurable for open-drain output when CCP2 is active on this pin.
PIC18F85J90 FAMILY TABLE 10-12: PORTE FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RE0/LCDBIAS1 RE0 0 O DIG LATE<0> data output. 1 I ST PORTE<0> data input. LCDBIAS1 — I ANA LCD module bias voltage input. RE1 0 O DIG LATE<1> data output. 1 I ST PORTE<1> data input. RE1/LCDBIAS2 RE3/COM0 RE4/COM1 RE5/COM2 RE6/COM3 RE7/CCP2/ SEG31 LCDBIAS2 — I ANA LCD module bias voltage input. RE3 0 O DIG LATE<3> data output.
PIC18F85J90 FAMILY 10.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTF is multiplexed with analog peripheral functions, as well as LCD segments. Pins RF1 through RF6 may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register.
PIC18F85J90 FAMILY TABLE 10-14: PORTF FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RF1/AN6/C2OUT/ SEG19 RF1 0 O DIG 1 I ST 1 I ANA AN6 RF2/AN7/C1OUT/ SEG20 RF3/AN8/SEG21 RF4/AN9/SEG22 RF5/AN10/CVREF/ SEG23 RF6/AN11/SEG24 RF7/AN5/SS/ SEG25 Legend: Description LATF<1> data output; not affected by analog input. PORTF<1> data input; disabled when analog input is enabled. A/D Input Channel 6. Default configuration on POR.
PIC18F85J90 FAMILY TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name PORTF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RF7 RF6 RF5 RF4 RF3 RF2 RF1 — 60 60 60 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 — TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 — ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 59 59 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1
PIC18F85J90 FAMILY 10.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISG and LATG. All pins on PORTG are digital only and tolerate voltages up to 5.5V. PORTG is multiplexed with both AUSART and LCD functions (Table 10-16). When operating as I/O, all PORTG pins have Schmitt Trigger input buffers. The RG1 pin is also configurable for open-drain output when the AUSART is active.
PIC18F85J90 FAMILY TABLE 10-16: PORTG FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RG0/LCDBIAS0 RG0 0 O DIG LATG<0> data output. 1 I ST LCDBIAS0 x I ANA LCD module bias voltage input. RG1 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2 1 O DIG Synchronous serial data output (AUSART module); takes priority over port data. CK2 1 O DIG Synchronous serial data input (AUSART module); user must configure as an input.
PIC18F85J90 FAMILY 10.9 Note: PORTH, LATH and TRISH Registers PORTH is available only on 80-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction and Data Latch registers are TRISH and LATH. All pins are digital only and tolerate voltages up to 5.5V. All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
PIC18F85J90 FAMILY TABLE 10-18: PORTH FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RH0 0 O DIG RH0/SEG47 LATH<0> data output. 1 I ST SEG47 x O ANA LCD Segment 47 output; disables all other pin functions. RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. SEG46 x O ANA LCD Segment 46 output; disables all other pin functions. RH2 0 O DIG LATH<2> data output. 1 I ST SEG45 x O ANA LCD Segment 45 output; disables all other pin functions.
PIC18F85J90 FAMILY 10.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction and Data Latch registers are TRISJ and LATJ. All pins on PORTJ are digital only and tolerate voltages up to 5.5V. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset.
PIC18F85J90 FAMILY TABLE 10-20: PORTJ FUNCTIONS Function TRIS Setting I/O I/O Type RJ0 RJ0 0 O DIG RJ1/SEG33 RJ1 Pin Name LATJ<0> data output. 1 I ST PORTJ<0> data input. 0 O DIG LATJ<1> data output. 1 I ST SEG33 x O ANA LCD Segment 33 output; disables all other pin functions. RJ2 0 O DIG LATJ<2> data output. 1 I ST SEG34 x O ANA LCD Segment 34 output; disables all other pin functions. RJ3 0 O DIG LATJ<3> data output. RJ2/SEG34 RJ3/SEG35 PORTJ<1> data input.
PIC18F85J90 FAMILY 11.
PIC18F85J90 FAMILY 11.1 Timer0 Operation internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”).
PIC18F85J90 FAMILY 11.3 Prescaler 11.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable.
PIC18F85J90 FAMILY NOTES: DS39770C-page 140 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 12.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Reset on CCP Special Event Trigger • Device clock status flag (T1RUN) REGISTER 12-1: A simplified block diagram of the Timer1 module is shown in Figure 12-1.
PIC18F85J90 FAMILY 12.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F85J90 FAMILY 12.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F85J90 FAMILY 12.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
PIC18F85J90 FAMILY EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F85J90 FAMILY NOTES: DS39770C-page 146 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 13.0 TIMER2 MODULE 13.1 Timer2 Operation • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional use as the shift clock for the MSSP module In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4).
PIC18F85J90 FAMILY 13.2 Timer2 Interrupt 13.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F85J90 FAMILY 14.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Module Reset on CCP Special Event Trigger REGISTER 14-1: A simplified block diagram of the Timer3 module is shown in Figure 14-1.
PIC18F85J90 FAMILY 14.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18F85J90 FAMILY 14.2 Timer3 16-Bit Read/Write Mode 14.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 14-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18F85J90 FAMILY NOTES: DS39770C-page 152 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F85J90 family devices have two CCP (Capture/Compare/PWM) modules, designated CCP1 and CCP2. Both modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. REGISTER 15-1: Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18F85J90 FAMILY 15.1 CCP Module Configuration Depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (Capture/Compare or PWM) sharing timer resources. The possible configurations are shown in Figure 15-1. Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register in turn is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte).
PIC18F85J90 FAMILY TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES CCP1 Mode CCP2 Mode Interaction Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different for each CCP. Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending upon which time base is used). Automatic A/D conversions on a trigger event can also be done.
PIC18F85J90 FAMILY 15.2 Capture Mode 15.2.3 SOFTWARE INTERRUPT In Capture mode, the CCPR2H:CCPR2L register pair captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on the CCP2 pin (RC1 or RE7, depending on device configuration). An event is defined as one of the following: When the Capture mode is changed, a false capture interrupt may be generated.
PIC18F85J90 FAMILY 15.3 Compare Mode 15.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPR2 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP2 pin can be: When the Generate Software Interrupt mode is chosen (CCP2M<3:0> = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP2IE bit is set. • • • • 15.3.
PIC18F85J90 FAMILY TABLE 15-3: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 57 IPEN — CM RI TO PD POR BOR 58 PIR3 — LCDIF RC2IF TX2IF — CCP2IF CCP1IF — 60 PIE3 — LCDIE RC2IE TX2IE — CCP2IE CCP1IE — 60 IPR3 — LCDIP RC2IP TX2IP — CCP2IP CCP1IP — 60 RCON PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF
PIC18F85J90 FAMILY 15.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP2 pin produces up to a 10-bit resolution PWM output. Since the CCP2 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to make the CCP2 pin an output. Note: A PWM output (Figure 15-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
PIC18F85J90 FAMILY 15.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits. Up to 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>.
PIC18F85J90 FAMILY 15.4.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR2L register and CCP2CON<5:4> bits. TABLE 15-5: Name INTCON 4. 5. Make the CCP2 pin an output by clearing the appropriate TRIS bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCP2 module for PWM operation.
PIC18F85J90 FAMILY NOTES: DS39770C-page 162 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 16.
PIC18F85J90 FAMILY 16.1 LCD Registers The LCDPS register, shown in Register 16-2, configures the LCD clock source prescaler and the type of waveform: Type-A or Type-B. Details on these features are provided in Section 16.2 “LCD Clock Source”, Section 16.3 “LCD Bias Generation” and Section 16.8 “LCD Waveform Generation”.
PIC18F85J90 FAMILY REGISTER 16-2: LCDPS: LCD PHASE REGISTER R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode Select bit When LMUX
PIC18F85J90 FAMILY REGISTER 16-3: LCDSEx: LCD SEGMENT ENABLE REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SE(n + 7) SE(n + 6) SE(n + 5) SE(n + 4) SE(n + 3) SE(n + 2) SE(n + 1) SE(n) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEG(n + 7):SEG(n): Segment Enable bits For LCDSE0: n = 0 For LCDSE1: n = 8 For LCDSE2: n = 16 For LCDSE3: n = 24 For LCDSE4: n = 32 For L
PIC18F85J90 FAMILY 16.1.2 LCD DATA REGISTERS Individual LCDDATA bits are named by the convention “SxxCy”, with “xx” as the segment number and “y” as the common number. The relationship is summarized in Table 16-2. The prototype LCDDATA register is shown in Register 16-4. Once the module is initialized for the LCD panel, the individual bits of the LCDDATA23:LCDDATA0 registers are cleared or set to represent a clear or dark pixel, respectively.
PIC18F85J90 FAMILY 16.2 LCD Clock Source The charge pump clock can use either the Timer1 oscillator or the INTRC source, as well as the 8 MHz INTOSC source (after being divided by 256 by a prescaler). The charge pump clock source is configured using the CKSEL<1:0> bits (LCDREG<1:0>). The LCD driver module generates its internal clock from 3 possible sources: • System clock (FOSC/4) • Timer1 oscillator • INTRC source 16.2.
PIC18F85J90 FAMILY 16.3 LCD Bias Generation 16.3.2 LCD VOLTAGE REGULATOR The LCD driver module is capable of generating the required bias voltages for LCD operation with a minimum of external components. This includes the ability to generate the different voltage levels required by the different bias types required by the LCD. The driver module can also provide bias voltages both above and below microcontroller VDD through the use of an on-chip LCD voltage regulator.
PIC18F85J90 FAMILY 16.3.3 BIAS CONFIGURATIONS M0 supports Static and 1/3 Bias types. Generation of the voltage levels for 1/3 Bias is handled automatically, but must be configured in software. PIC18F85J90 family devices have four distinct circuit configurations for LCD bias generation: • • • • M0 is enabled by selecting a valid regulator clock source (CKSEL<1:0> set to any value except ‘00’) and setting the CPEN bit. If static Bias type is required, the MODE13 bit must be cleared.
PIC18F85J90 FAMILY 16.3.3.3 M2 (Resistor Ladder with Software Contrast) configuration of the resistor ladder. Most applications using M2 will use a 1/3 or 1/2 Bias type. While Static Bias can also be used, it offers extremely limited contrast range and additional current consumption over other bias generation modes. M2 operation also uses the LCD regulator but disables the charge pump. The regulator’s internal voltage reference remains active as a way to regulate contrast.
PIC18F85J90 FAMILY 16.3.3.4 M3 (Hardware Contrast) In M3, the LCD regulator is completely disabled. Like M2, LCD bias levels are tied to AVDD, and are generated using an external divider. The difference is that the internal voltage reference is also disabled and the bottom of the ladder is tied to ground (VSS); see Figure 16-5. The value of the resistors and the difference between VSS and VDD determine the contrast range; no software adjustment is possible.
PIC18F85J90 FAMILY 16.3.4 DESIGN CONSIDERATIONS FOR THE LCD CHARGE PUMP When designing applications that use the LCD regulator with the charge pump enabled, users must always consider both the dynamic current and RMS (static) current requirements of the display, and what the charge pump can deliver.
PIC18F85J90 FAMILY 16.7 LCD Frame Frequency 16.8 The rate at which the COM and SEG outputs changes is called the LCD frame frequency. Frame frequency is set by the LP<3:0> bits (LCDPS<3:0>), and is also affected by the Multiplex mode being used. The relationship between the Multiplex mode, LP bits setting and frame rate is shown in Table 16-4 and Table 16-5.
PIC18F85J90 FAMILY FIGURE 16-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE V1 COM0 V0 COM0 V1 SEG0 V0 V1 SEG1 SEG0 SEG2 SEG7 SEG6 SEG5 SEG4 SEG3 SEG1 V0 V1 V0 COM0-SEG0 -V1 COM0-SEG1 V0 1 Frame 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM1 V2 COM0 COM1 V1 V0 V2 V1 SEG0 V0 SEG0 SEG1 SEG2 SEG3 V2 V1 SEG1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS39770C-page 176 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 V1 COM0 COM1 V0 COM0 V2 COM1 V1 V0 V2 SEG0 V1 SEG0 SEG1 SEG2 SEG3 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS39770C-page 178 -V3 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 V0 COM1 COM0 V2 COM2 V1 V0 V2 SEG0 SEG2 V1 SEG0 SEG1 SEG2 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS39770C-page 180 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 COM1 V0 COM0 V2 COM2 V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 SEG2 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 1 Frame DS39770C-page 182 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 2 Frames 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame DS39770C-page 184 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY FIGURE 16-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 2 Frames 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 16.9 LCD Interrupts When the LCD driver is running with Type-B waveforms, and the LMUX<1:0> bits are not equal to ‘00’, there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames.
PIC18F85J90 FAMILY 16.10 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by the SLPEN bit (LCDCON<6>). Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current consumption mode.
PIC18F85J90 FAMILY 16.11 Configuring the LCD Module 6. The following is the sequence of steps to configure the LCD module. 1. 2. 3. 4. 5. Select the frame clock prescale using bits, LP<3:0> (LCDPS<3:0>). Configure the appropriate pins to function as segment drivers using the LCDSEx registers. Configure the appropriate pins as inputs using the TRISx registers.
PIC18F85J90 FAMILY TABLE 16-6: Name REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR3 — LCDIF RC2IF TX2IF — CCP2IF CCP1IF — 60 PIE3 — LCDIE RC2IE TX2IE — CCP2IE CCP1IE — 60 IPR3 — LCDIP RC2IP TX2IP — CCP2IP CCP1IP — 60 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 4 IPEN — CM RI TO PD POR BOR 58 S47C3 S46C3 S45C3 S44C3 S43C3 S42C3 S41C3 S40C3 61 LCDDATA22 S39C
PIC18F85J90 FAMILY NOTES: DS39770C-page 190 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 17.0 17.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Figure 17-1 shows the block diagram of the MSSP module when operating in SPI mode. Note: Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F85J90 FAMILY 17.3.1 REGISTERS SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. Each MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC18F85J90 FAMILY REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the p
PIC18F85J90 FAMILY 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18F85J90 FAMILY 17.3.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18F85J90 FAMILY 17.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18F85J90 FAMILY 17.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit (SSPCON1<4>). While in Slave mode, the external clock is supplied by the external clock source on the SCK pin.
PIC18F85J90 FAMILY FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2 SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 7 bit 6 bit 5 bit
PIC18F85J90 FAMILY 17.3.9 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTRC source. See Section 3.3 “Clock Sources and Oscillator Switching” for additional information.
PIC18F85J90 FAMILY 17.4 I2C Mode 17.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Note: Disabling the MSSP module by clearing the SSPEN (SSPCON1<5>) bit may not reset the module.
PIC18F85J90 FAMILY REGISTER 17-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 R-0 R0 R-0 D/A (1) (1) R/W UA BF P S bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Sp
PIC18F85J90 FAMILY REGISTER 17-4: R/W-0 WCOL SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not
PIC18F85J90 FAMILY REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode.
PIC18F85J90 FAMILY REGISTER 17-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General ca
PIC18F85J90 FAMILY 17.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I 2C operation.
PIC18F85J90 FAMILY 17.4.3.2 Address Masking Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-bit mode and up to 63 addresses in 10-bit mode (see Example 17-2). The I2C Slave behaves the same way whether address masking is used or not.
PIC18F85J90 FAMILY 17.4.3.3 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON1<6>), is set.
DS39770C-page 208 CKP 2 A6 3 A5 4 A4 5 A3 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
2010 Microchip Technology Inc. Note CKP 2 A6 3 4 X 5 A3 Receiving Address A5 6 X 1 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D7 x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
DS39770C-page 210 2 Data in sampled 1 A6 CKP (SSPxCON1<4>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 R/W = 1 9 ACK 3 D5 4 5 D3 SSPxBUF is written in software 6 D2 Transmitting Data D4 Cleared in software 2 D6 CKP is set in software Clear by reading SCLx held low while CPU responds to SSPxIF 1 D7 7 8 D0 9 From SSPxIF ISR D1 ACK 1 D7 4 D4 5 D3 Cleared in software 3 D5 6 D2 CKP is set in software S
2010 Microchip Technology Inc.
DS39770C-page 212 2 1 Note 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 ACK 2 X 4 5 A3 6 A2 Cleared in software 3 A5 4 5 6 7 8 9 1 2 4 5 6 D3 D2 Cleared in software 3 D5 D4 Receive Data Byte D1 D0 ACK D7 D6 Cleared in software 3 D2 Cleared by hardware when SSPADD is updated with high byte of address 2 D6 D5 D4 D3 Note that the Most Significant bits of the address are not affected by the
2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 17.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 17.4.4.
PIC18F85J90 FAMILY 17.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has FIGURE 17-14: already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS39770C-page 216 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S A7 2 A6 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
2010 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) SSPIF (PIR1<3>) 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18F85J90 FAMILY 17.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F85J90 FAMILY MASTER MODE Note: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur.
PIC18F85J90 FAMILY 17.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18F85J90 FAMILY 17.4.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 17-19). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F85J90 FAMILY 17.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 17-20: SDA SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18F85J90 FAMILY 17.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC18F85J90 FAMILY 17.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPADD<6:0> and begins counting.
PIC18F85J90 FAMILY 17.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
DS39770C-page 226 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting D
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PIC18F85J90 FAMILY 17.4.12 ACKNOWLEDGE SEQUENCE TIMING 17.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18F85J90 FAMILY 17.4.14 SLEEP OPERATION 17.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 17.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.4.
PIC18F85J90 FAMILY 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 17-28). SCL is sampled low before SDA is asserted low (Figure 17-29). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 17-30).
PIC18F85J90 FAMILY FIGURE 17-29: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F85J90 FAMILY 17.4.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 17-31). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F85J90 FAMILY 17.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 17-33).
PIC18F85J90 FAMILY TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 — ADIF RC1IF TX1IF SSPIF — TMR2IF TMR1IF 60 PIE1 — ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE 60 IPR1 — ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP 60 PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF — 60 PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —
PIC18F85J90 FAMILY 18.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) PIC18F85J90 family devices have three serial I/O modules: the MSSP module, discussed in the previous chapter and two Universal Synchronous Asynchronous Receiver Transmitter (USART) modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.
PIC18F85J90 FAMILY REGISTER 18-1: TXSTA1: EUSART TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F85J90 FAMILY REGISTER 18-2: RCSTA1: EUSART RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-b
PIC18F85J90 FAMILY REGISTER 18-3: BAUDCON1: BAUD RATE CONTROL REGISTER 1 R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No B
PIC18F85J90 FAMILY 18.2 EUSART Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>) selects 16-bit mode. The SPBRGH1:SPBRG1 register pair controls the period of a free-running timer. In Asynchronous mode, BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F85J90 FAMILY EXAMPLE 18-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1)) Solving for SPBRGH1:SPBRG1: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F85J90 FAMILY TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz Actual Rate (K) FOSC = 10.000 MHz Actual Rate (K) FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.
PIC18F85J90 FAMILY TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.
PIC18F85J90 FAMILY 18.2.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 18-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. While the ABD sequence takes place, the EUSART state machine is held in Idle.
PIC18F85J90 FAMILY FIGURE 18-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h 001Ch Start RX1 pin Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto-Cleared Set by User ABDEN bit RC1IF bit (Interrupt) Read RCREG1 SPBRG1 XXXXh 1Ch SPBRGH1 XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F85J90 FAMILY 18.3 EUSART Asynchronous Mode Once the TXREG1 register transfers the data to the TSR register (occurs in one TCY), the TXREG1 register is empty and the TX1IF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF will be set regardless of the state of TX1IE; it cannot be cleared in software.
PIC18F85J90 FAMILY FIGURE 18-4: ASYNCHRONOUS TRANSMISSION Write to TXREG1 Word 1 BRG Output (Shift Clock) TX1 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX1IF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG1 Word 2 Word 1 BRG Output (Shift Clock) TX1 (pin) Start bit bit 1 1 TCY TX1IF bit (Interrupt Reg.
PIC18F85J90 FAMILY 18.3.2 EUSART ASYNCHRONOUS RECEIVER 18.3.3 The receiver block diagram is shown in Figure 18-6. The data is received on the RX1 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F85J90 FAMILY FIGURE 18-7: ASYNCHRONOUS RECEPTION Start bit RX1 (pin) bit 0 bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG1 Word 1 RCREG1 RCREG1 Read Rcv Buffer Reg bit 7/8 RC1IF (Interrupt Flag) OERR bit CREN bit Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F85J90 FAMILY 18.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up, due to activity on the RX1/DT1 line, while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>).
PIC18F85J90 FAMILY 18.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
PIC18F85J90 FAMILY 18.4 EUSART Synchronous Master Mode Once the TXREG1 register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG1 is empty and the TX1IF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is set regardless of the state of enable bit TX1IE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG1 register.
PIC18F85J90 FAMILY FIGURE 18-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 2 bit 1 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 Reg TX1IF bit TRMT bit TXEN bit TABLE 18-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR1 — ADIF RC1IF TX1IF SSPIF — TMR2IF TMR1IF 60 PIE1 — ADIE RC1IE TX1IE S
PIC18F85J90 FAMILY 18.4.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA1<5>), or the Continuous Receive Enable bit, CREN (RCSTA1<4>). Data is sampled on the RX1 pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F85J90 FAMILY 18.5 EUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 18.5.
PIC18F85J90 FAMILY 18.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode, and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F85J90 FAMILY NOTES: DS39770C-page 256 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 19.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is very similar in function to the Enhanced USART module, discussed in the previous chapter. It is provided as an additional channel for serial communication with external devices, for those situations that do not require auto-baud detection or LIN/J2602 bus support.
PIC18F85J90 FAMILY REGISTER 19-1: TXSTA2: AUSART TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F85J90 FAMILY REGISTER 19-2: RCSTA2: AUSART RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX2/DT2 and TX2/CK2 (TXEN = 1) pins as serial port pins) 0 = Serial port disabled
PIC18F85J90 FAMILY 19.2 AUSART Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit generator that supports both the Asynchronous and Synchronous modes of the AUSART. The SPBRG2 register controls the period of a free-running timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, BRGH is ignored. Table 19-1 shows the formula for computation of the baud rate for different AUSART modes, which only apply in Master mode (internally generated clock).
PIC18F85J90 FAMILY TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES BRGH = 0 FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — 1.221 — 1.73 1.73 255 2.404 0.16 64 9.766 19.531 1.73 31 57.6 56.818 -1.36 115.2 125.000 8.51 BAUD RATE (K) Actual Rate (K) % Error 0.3 1.2 — — — — 2.4 2.441 9.6 9.615 19.2 FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — 255 — 1.202 — 0.16 0.16 129 2.404 1.73 31 9.766 19.531 1.73 15 10 62.500 8.
PIC18F85J90 FAMILY 19.3 AUSART Asynchronous Mode Once the TXREG2 register transfers the data to the TSR register (occurs in one TCY), the TXREG2 register is empty and the TX2IF flag bit (PIR3<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF will be set regardless of the state of TX2IE; it cannot be cleared in software.
PIC18F85J90 FAMILY FIGURE 19-2: ASYNCHRONOUS TRANSMISSION Write to TXREG2 Word 1 BRG Output (Shift Clock) TX2 (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TX2IF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 19-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG2 Word 2 Word 1 BRG Output (Shift Clock) TX2 (pin) Start bit bit 1 1 TCY TX2IF bit (Interrupt Reg.
PIC18F85J90 FAMILY 19.3.2 AUSART ASYNCHRONOUS RECEIVER 19.3.3 The receiver block diagram is shown in Figure 19-4. The data is received on the RX2 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F85J90 FAMILY FIGURE 19-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX2 (pin) bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG2 Word 1 RCREG2 Read Rcv Buffer Reg RCREG2 bit 7/8 RC2IF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F85J90 FAMILY 19.4 AUSART Synchronous Master Mode Once the TXREG2 register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG2 is empty and the TX2IF flag bit (PIR3<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is set regardless of the state of enable bit, TX2IE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG2 register.
PIC18F85J90 FAMILY FIGURE 19-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX2/DT2 pin bit 0 bit 1 bit 2 bit 6 bit 7 TX2/CK2 pin Write to TXREG2 Reg TX2IF bit TRMT bit TXEN bit TABLE 19-6: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page INT0IE RBIE TMR0IF INT0IF RBIF 57 PIR3 — LCDIF RC2IF TX2IF — CCP2IF CCP1IF — 60 PIE3 — LCDIE RC2IE TX2IE — CCP2IE C
PIC18F85J90 FAMILY 19.4.2 AUSART SYNCHRONOUS MASTER RECEPTION 4. 5. 6. If interrupts are desired, set enable bit, RC2IE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RC2IF, will be set when reception is complete and an interrupt will be generated if the enable bit, RC2IE, was set. 8. Read the RCSTA2 register to get the 9th bit (if enabled) and determine if any error occurred during reception.
PIC18F85J90 FAMILY 19.5 AUSART Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA2<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK2 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 19.5.
PIC18F85J90 FAMILY 19.5.2 AUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of Sleep or any Idle mode, and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep, or any Idle mode, then a word may be received while in this low-power mode.
PIC18F85J90 FAMILY 20.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 12 inputs for all PIC18F85J90 family devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The ADCON0 register, shown in Register 20-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 20-2, configures the functions of the port pins.
PIC18F85J90 FAMILY REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
PIC18F85J90 FAMILY REGISTER 20-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110
PIC18F85J90 FAMILY The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode.
PIC18F85J90 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 20.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion.
PIC18F85J90 FAMILY 20.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F85J90 FAMILY 20.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F85J90 FAMILY 20.5 A/D Conversions 20.6 Figure 20-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. An A/D conversion can be started by the “Special Event Trigger” of the CCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set).
PIC18F85J90 FAMILY 20.7 A/D Converter Calibration The A/D Converter in the PIC18F85J90 family of devices includes a self-calibration feature which compensates for any offset generated within the module. The calibration process is automated and is initiated by setting the ADCAL bit (ADCON0<7>). The next time the GO/DONE bit is set, the module will perform a “dummy” conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for offset.
PIC18F85J90 FAMILY NOTES: DS39770C-page 280 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 21.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with pins RF1 through RF6, as well as the on-chip voltage reference (see Section 22.0 “Comparator Voltage Reference Module”). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register.
PIC18F85J90 FAMILY 21.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 21-1. Bits, CM<2:0> of the CMCON register, are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 21-1: RF4/AN9/ SEG22 RF3/AN8/ SEG21 A A RF4/AN9/ SEG22 RF3/AN8/ SEG21 Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur.
PIC18F85J90 FAMILY 21.2 Comparator Operation 21.3.2 A single comparator is shown in Figure 21-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F85J90 FAMILY + COMPARATOR OUTPUT BLOCK DIAGRAM To RF1 or RF2 Pin - Port Pins MULTIPLEX FIGURE 21-3: D Q Bus Data CxINV Read CMCON EN D Q EN CL From Other Comparator Reset 21.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC18F85J90 FAMILY 21.9 Analog Input Connection Considerations range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. A simplified circuit for an analog input is shown in Figure 21-4.
PIC18F85J90 FAMILY NOTES: DS39770C-page 286 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 22.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 22-1.
PIC18F85J90 FAMILY FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR<3:0> R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 22.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 22-1) keep CVREF from approaching the reference source rails.
PIC18F85J90 FAMILY FIGURE 22-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F85J90 CVREF Module R(1) Voltage Reference Output Impedance Note 1: TABLE 22-1: Name CVRCON + – RF5 CVREF Output R is dependent upon the Comparator Voltage Reference bits, CVRCON<5> and CVRCON<3:0>.
PIC18F85J90 FAMILY NOTES: DS39770C-page 290 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 23.0 SPECIAL FEATURES OF THE CPU PIC18F85J90 family devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F85J90 FAMILY TABLE 23-2: CONFIGURATION BITS AND DEVICE IDs File Name 300000h CONFIG1L Default/ Unprogrammed Value(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEBUG XINST STVREN — — — — WDTEN 111- ---1 (2) (2) (2) (2) (3) 300001h CONFIG1H — 300002h CONFIG2L IESO FCMEN — — 300003h CONFIG2H —(2) —(2) —(2) —(2) 300005h CONFIG3H —(2) —(2) —(2) —(2) — — — CCP2MX 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(4) 3FFFFFh DE
PIC18F85J90 FAMILY REGISTER 23-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN — — — — WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins 0 = Background
PIC18F85J90 FAMILY REGISTER 23-3: R/WO-1 IESO bit 7 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 FCMEN — — — FOSC2 FOSC1 FOSC0 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is d
PIC18F85J90 FAMILY REGISTER 23-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 (1) (1) (1) (1) — — — — R/WO-1 R/WO-1 R/WO-1 R/WO-1 WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 0 bit 7 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed bit 7-4 bit 3-0 Note 1: U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Unimplemented: Read as ‘0’ WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 =
PIC18F85J90 FAMILY REGISTER 23-6: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F85J90 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit bit 7-5 DEV<2:0>: Device ID bits 111 = PIC18F85J90 101 = PIC18F84J90 100 = PIC18F83J90 011 = PIC18F65J90 001 = PIC18F64J90 000 = PIC18F63J90 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision.
PIC18F85J90 FAMILY 23.2 Watchdog Timer (WDT) For PIC18F85J90 family devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexor, controlled by the WDTPS bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.
PIC18F85J90 FAMILY REGISTER 23-8: R/W-0 (1) REGSLP WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — SWDTEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared REGSLP: Voltage Regulator Low-Power Operation Enable bit(1) 1 = On-chip regulator enters low-power operation when device enters Sleep mode 0 = On-chip regulator continues to operate normally in Sleep
PIC18F85J90 FAMILY 23.3 On-Chip Voltage Regulator All of the PIC18F85J90 family devices power their core digital logic at a nominal 2.5V. For designs that are required to operate at a higher typical voltage, such as 3.3V, all devices in the PIC18F85J90 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins.
PIC18F85J90 FAMILY 23.3.2 ON-CHIP REGULATOR AND BOR The REGSLP bit is automatically cleared by hardware when a Low-Voltage Detect condition occurs. The REGSLP bit can be set again in software, which would continue to keep the voltage regulator in Low-Power mode. This, however, is not recommended if any write operations to the Flash will be performed. When the on-chip regulator is enabled, PIC18F85J90 family devices also have a simple Brown-out Reset capability.
PIC18F85J90 FAMILY 23.4.1 SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 4.1.4 “Multiple Sleep Commands”). In practice, this means that user code can change the SCS<1:0> bit settings or issue SLEEP instructions before the OST times out.
PIC18F85J90 FAMILY FIGURE 23-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 23.5.2 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode.
PIC18F85J90 FAMILY 23.6 Program Verification and Code Protection For all devices in the PIC18F85J90 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 23.6.
PIC18F85J90 FAMILY NOTES: DS39770C-page 304 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY 24.0 INSTRUCTION SET SUMMARY The PIC18F85J90 family of devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 24.
PIC18F85J90 FAMILY TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F85J90 FAMILY FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE
PIC18F85J90 FAMILY TABLE 24-2: PIC18F85J90 FAMILY INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s, f d MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d,
PIC18F85J90 FAMILY TABLE 24-2: PIC18F85J90 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F85J90 FAMILY TABLE 24-2: PIC18F85J90 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
PIC18F85J90 FAMILY 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F85J90 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F85J90 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 n 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F85J90 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F85J90 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number, ‘2n’, is added to the PC.
PIC18F85J90 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number, ‘2n’, is added to the PC.
PIC18F85J90 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number, ‘2n’, to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F85J90 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F85J90 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted.
PIC18F85J90 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F85J90 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F85J90 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: f dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F85J90 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F85J90 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>; C =1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: 0000 0000 0000 0111 Description: DAW adjusts
PIC18F85J90 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F85J90 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F85J90 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F85J90 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F85J90 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F85J90 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Status Affected: None Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F85J90 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F85J90 FAMILY MULLW Multiply Literal with W MULWF Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte.
PIC18F85J90 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F85J90 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F85J90 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F85J90 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded with the
PIC18F85J90 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine.
PIC18F85J90 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F85J90 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) dest, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F85J90 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F85J90 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F85J90 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F85J90 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Status Affected: None Encoding: Description: 0000 0000 0000 Before Instruction TABLAT TBLPTR MEMORY(
PIC18F85J90 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A35
PIC18F85J90 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F85J90 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F85J90 FAMILY 24.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions are provided in Section 24.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 24-1 (page 306) apply to both the standard and extended PIC18 instruction sets.
PIC18F85J90 FAMILY 24.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: Operation: FSR(f) + k FSR(f) FSR2 + k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F85J90 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F85J90 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0k 255 Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.
PIC18F85J90 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSRf – k FSRf FSR2 – k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F85J90 FAMILY 24.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F85J90 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the valu
PIC18F85J90 FAMILY 24.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F85J90 family family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F85J90 FAMILY 25.
PIC18F85J90 FAMILY 25.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 25.
PIC18F85J90 FAMILY 25.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F85J90 FAMILY 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F85J90 FAMILY 26.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ....................................
PIC18F85J90 FAMILY FIGURE 26-1: PIC18F85J90 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (INDUSTRIAL)(1) 4.0V 3.6V Voltage (VDD) 3.5V 3.0V PIC18F6XJ90/8XJ90 2.5V 2.35V 2.0V 0 Note 1: 8 MHz Frequency 40 MHz When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset before VDD reaches a level at which full-speed operation is not possible. FIGURE 26-2: PIC18F85J90 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL)(1,2) 3.
PIC18F85J90 FAMILY 26.1 DC Characteristics: Supply Voltage PIC18F85J90 Family (Industrial) PIC18F85J90 Family (Industrial) Param Symbol No. D001 VDD Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Characteristic Supply Voltage D001B VDDCORE External Supply for Microcontroller Core Min Typ Max Units VDDCORE 2.0 — — 3.6 3.6 V V ENVREG tied to VSS ENVREG tied to VDD 2.0 — 2.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No. Power-Down and Supply Current PIC18F85J90 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 0.2 0.9 µA -40°C 0.1 0.9 µA +25°C 0.3 3 µA +60°C 2.4 5 µA +85°C 0.5 0.9 µA -40°C 0.1 0.9 µA +25°C 0.4 3 µA +60°C 2.7 5 µA +85°C 2.7 6 µA -40°C 3.5 6 µA +25°C 4.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No. Power-Down and Supply Current PIC18F85J90 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 6.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No. Power-Down and Supply Current PIC18F85J90 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions Supply Current (IDD)(2) All devices All devices All devices All devices All devices All devices All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 7: 2.4 8 µA -40°C 2.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No. Power-Down and Supply Current PIC18F85J90 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units 2.8 3.8 mA Conditions Supply Current (IDD)(2) All devices All devices All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 7: -40°C 3.02 3.8 mA +25°C 3.01 4.5 mA +85°C 4.5 5.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No. Power-Down and Supply Current PIC18F85J90 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device Typ Max Units Conditions 10.5 22 µA -40°C 13.4 28 µA +25°C 17.6 40 µA +85°C 13.2 30 µA -40°C 16.
PIC18F85J90 FAMILY 26.2 DC Characteristics: PIC18F85J90 Family (Industrial) Param No. D022 (IWDT) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Device D025 (IOSCB) D026 (IAD) Timer1 Oscillator A/D Converter Note 1: 2: 3: 4: 5: 6: 7: Typ Max Units Conditions Module Differential Currents (IWDT, ILCD, IOSCB, IAD) Watchdog Timer 1.
PIC18F85J90 FAMILY 26.3 DC Characteristics:PIC18F84J90 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 3.3V — 0.8 V 3.3V VDD 3.6V Input Low Voltage All I/O Ports: D030 with TTL Buffer D30A D031 with Schmitt Trigger Buffer D031A RC3 and RC4 D031B VSS 0.2 VDD V VSS 0.
PIC18F85J90 FAMILY 26.3 DC Characteristics:PIC18F84J90 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic Min Max Units Conditions PORTA, PORTF, PORTG, PORTH — 0.4 V IOL = 3.4 mA, VDD = 3.3V, -40C to +85C PORTD, PORTE, PORTJ — 0.4 V IOL = 3.4 mA, VDD = 3.3V, -40C to +85C PORTB, PORTC — 0.4 V IOL = 8.5 mA, VDD = 3.
PIC18F85J90 FAMILY TABLE 26-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Program Flash Memory D130 EP Cell Endurance 100 1K — E/W -40C to +85C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132 VPEW Voltage for Self-Timed Erase or Write: VDD 2.35 — 3.
PIC18F85J90 FAMILY TABLE 26-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V VDD 3.6V, -40°C TA +85°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D310 VRES Resolution VDD/24 — VDD/32 LSb D311 VRAA Absolute Accuracy — — 1/2 LSb D312 VRUR Unit Resistor Value (R) — 2k — D313 TSET Settling Time(1) — — 10 s Note 1: Comments Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’.
PIC18F85J90 FAMILY 26.4 26.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F85J90 FAMILY 26.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 26-6 apply to all timing specifications unless otherwise noted. Figure 26-3 specifies the load conditions for the timing specifications. TABLE 26-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Operating voltage VDD range as described in Section 26.1 and Section 26.3.
PIC18F85J90 FAMILY 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 26-7: Param. No.
PIC18F85J90 FAMILY TABLE 26-8: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms CLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 3.3V, 25C, unless otherwise stated.
PIC18F85J90 FAMILY FIGURE 26-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 26-3 for load conditions. TABLE 26-10: CLKO AND I/O TIMING REQUIREMENTS Param No.
PIC18F85J90 FAMILY FIGURE 26-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 26-3 for load conditions. TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No.
PIC18F85J90 FAMILY FIGURE 26-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 26-3 for load conditions. TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F85J90 FAMILY FIGURE 26-8: CAPTURE/COMPARE/PWM TIMINGS (CCP1, CCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 26-3 for load conditions. TABLE 26-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1, CCP2 MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18F85J90 FAMILY FIGURE 26-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 26-3 for load conditions. TABLE 26-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F85J90 FAMILY FIGURE 26-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 26-3 for load conditions. TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F85J90 FAMILY FIGURE 26-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 MSb In SDI 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 26-3 for load conditions. TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F85J90 FAMILY FIGURE 26-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - - 1 LSb 75, 76 SDI MSb In 77 bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 26-3 for load conditions. TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F85J90 FAMILY I2C™ BUS START/STOP BITS TIMING FIGURE 26-13: SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-3 for load conditions. TABLE 26-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F85J90 FAMILY TABLE 26-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR 103 TF TSU:STA 90 THD:STA 91 THD:DAT 106 TSU:DAT 107 TSU:STO 92 109 TAA 110 TBUF D102 CB Note 1: 2: Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s MSSP Module 1.5 TCY — s 100 kHz mode 4.7 — s Conditions 400 kHz mode 1.3 — s MSSP Module 1.
PIC18F85J90 FAMILY MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 26-15: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 26-3 for load conditions. TABLE 26-20: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F85J90 FAMILY TABLE 26-21: MSSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Clock High Time Min Max 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1,2) 2(TOSC)(BRG + 1) — Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — (1,2) 2(TOSC)(BRG + 1) — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns — 300 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.
PIC18F85J90 FAMILY FIGURE 26-17: EUSART/AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 26-3 for load conditions. TABLE 26-22: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F85J90 FAMILY TABLE 26-24: A/D CONVERTER CHARACTERISTICS: PIC18F85J90 FAMILY (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units — — 10 bits Conditions A01 NR Resolution A03 EIL Integral Linearity Error — — <±1 LSb VREF 3.0V A04 EDL Differential Linearity Error — — <±1 LSb VREF 3.0V A06 EOFF Offset Error — — <±3 LSb VREF 3.0V A07 EGN Gain Error — — <±3 LSb VREF 3.
PIC18F85J90 FAMILY FIGURE 26-19: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY (Note 1) ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F85J90 FAMILY 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F85J90 FAMILY 27.2 Package Details The following sections give the technical details of the packages.
PIC18F85J90 FAMILY ' ( !" #$ % & 3 & ' !& " & 4 && 255*** ' '5 2010 Microchip Technology Inc.
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PIC18F85J90 FAMILY NOTES: DS39770C-page 398 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY APPENDIX A: REVISION HISTORY Revision A (July 2006) Original data sheet for PIC18F85J90 family devices. Revision B (March 2007) Updated power-down and supply current electrical characteristics and package details illustrations. Revision C (January 2010) Updated electrical characteristics and package detail illustrations. Minor text edits throughout document. 2010 Microchip Technology Inc.
PIC18F85J90 FAMILY APPENDIX B: MIGRATION BETWEEN HIGH-END DEVICE FAMILIES ences which should be considered when migrating an application across device families to achieve a new design goal. These are summarized in Table B-1. The areas of difference, which could be a major impact on migration, are discussed in greater detail later in this section. Devices in the PIC18F85J90 and PIC18F8490 families are very similar in their functions and feature sets.
PIC18F85J90 FAMILY B.1 Power Requirement Differences The most significant difference between the PIC18F85J90 and PIC18F8490 device families is the power requirements. PIC18F85J90 family devices are designed on a smaller process. This results in lower maximum voltage and higher leakage current. The operating voltage range for PIC18F85J90 devices is 2.0V to 3.6V. In addition, these devices have split power requirements: one for the core logic and one for the I/O.
PIC18F85J90 FAMILY B.4 Pin Differences B.5 Other Peripherals Besides the LCD pinout differences already described, there are other differences in the pinouts between the PIC18F85J90 and the PIC18F8490 families: Peripherals must also be considered when making a conversion between the PIC18F85J90 and the PIC18F8490 families: • Input voltage tolerance • Output current capabilities • Available I/O • A/D Converter: The converter for PIC18F85J90 devices require a calibration step prior to normal operation.
PIC18F85J90 FAMILY INDEX A A/D ................................................................................... 271 A/D Converter Interrupt, Configuring ....................... 275 Acquisition Requirements ........................................ 276 ADCAL Bit ................................................................ 279 ADCON0 Register .................................................... 271 ADCON1 Register .................................................... 271 ADCON2 Register .................
PIC18F85J90 FAMILY Reads from Flash Program Memory .......................... 91 Resistor Ladder Configurations for M2 .................... 171 Resistor Ladder Configurations for M3 .................... 172 Single Comparator ................................................... 283 SPI Master/Slave Connection .................................. 195 Table Read Operation ................................................ 87 Table Write Operation ................................................
PIC18F85J90 FAMILY Core Features Easy Migration ............................................................. 9 Extended Instruction Set .............................................. 9 Memory Options ........................................................... 9 nanoWatt Technology .................................................. 9 Oscillator Options and Features .................................. 9 CPFSEQ .......................................................................... 322 CPFSGT ..............
PIC18F85J90 FAMILY Flash Program Memory ...................................................... 87 Associated Registers ................................................. 95 Control Registers ....................................................... 88 EECON1 and EECON2 ..................................... 88 TABLAT (Table Latch) Register ......................... 90 TBLPTR (Table Pointer) Register ...................... 90 Erase Sequence ........................................................ 92 Erasing ....
PIC18F85J90 FAMILY LFSR ........................................................................ 329 MOVF ....................................................................... 329 MOVFF .................................................................... 330 MOVLB .................................................................... 330 MOVLW ................................................................... 331 MOVWF ................................................................... 331 MULLW ..........
PIC18F85J90 FAMILY MSSP ACK Pulse ........................................................ 205, 207 Control Registers (general) ...................................... 191 Module Overview ..................................................... 191 SSPBUF Register .................................................... 196 SSPSR Register ...................................................... 196 MULLW ............................................................................ 332 MULWF ...........................
PIC18F85J90 FAMILY PORTA Associated Registers ............................................... 117 LATA Register .......................................................... 116 PORTA Register ...................................................... 116 TRISA Register ........................................................ 116 PORTB Associated Registers ............................................... 120 LATB Register .......................................................... 118 PORTB Register ................
PIC18F85J90 FAMILY CONFIG2H (Configuration 2 High) .......................... 295 CONFIG2L (Configuration 2 Low) ............................ 294 CONFIG3H (Configuration 3 High) .......................... 295 CVRCON (Comparator Voltage Reference Control) ........................................... 287 DEVID1 (Device ID Register 1) ................................ 296 DEVID2 (Device ID Register 2) ................................ 296 EECON1 (EEPROM Control 1) ..................................
PIC18F85J90 FAMILY Timer0 .............................................................................. 137 Associated Registers ............................................... 139 Clock Source Select (T0CS Bit) ............................... 138 Operation ................................................................. 138 Overflow Interrupt .................................................... 139 Prescaler .................................................................. 139 Switching Assignment .....
PIC18F85J90 FAMILY Transition for Entry to SEC_RUN Mode .................... 45 Transition for Entry to Sleep Mode ............................ 47 Transition for Two-Speed Start-up (INTRC to HSPLL) ........................................... 300 Transition for Wake From Idle to Run Mode .............. 48 Transition for Wake From Sleep (HSPLL) ................. 47 Transition From RC_RUN Mode to PRI_RUN Mode .................................................
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PIC18F85J90 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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