Datasheet

PIC18F6585/8585/6680/8680

DS30491D-page 94  2003-2013 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

EBDIS

(1)

—WAIT1WAIT0— —WM1WM0

bit 7 bit 0

bit 7 EBDIS: External Bus Disable bit

(1)

1 = External system bus disabled, all external bus drivers are mapped as I/O ports

0 = External system bus enabled and I/O ports are disabled

Note 1: This bit is ignored when device is accessing external memory either to fetch an

instruction or perform TBLRD/TBLWT.

bit 6 Unimplemented: Read as ‘0’

bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits

11 = Table reads and writes will wait 0 T

10 = Table reads and writes will wait 1 TCY

01 = Table reads and writes will wait 2 TCY

00 = Table reads and writes will wait 3 TCY

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 WM<1:0>: TBLWT Operation with 16-bit Bus bits

1x = Word Write mode: LSB and MSB word output, WRH active when MSB written

01 = Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH

and (UB or LB)

will activate

00 = Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH

or WRL will activate

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: The MEMCON register is held in Reset in Microcontroller mode.

18F8680.book Page 94 Tuesday, January 29, 2013 1:32 PM