Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 439
PIC18F6585/8585/6680/8680
FIGURE 27-17: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 27-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param.
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SS
 to SCK  or SCK  Input TCY —ns
71 T
SCH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDI Data Input to SCK Edge 100 — ns
73A T
B2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDI Data Input to SCK Edge 100 — ns
75 T
DOR SDO Data Output Rise Time PIC18FXX8X — 25 ns
PIC18LFXX8X 45 ns
76 T
DOF SDO Data Output Fall Time — 25 ns
77 T
SSH2DOZSS  to SDO Output High-Impedance 10 50 ns
78 T
SCR SCK oUtput Rise Time (Master mode) PIC18FXX8X — 25 ns
PIC18LFXX8X 45 ns
79 T
SCF SCK Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDO Data Output Valid after SCK Edge PIC18FXX8X — 50 ns
PIC18LFXX8X 100 ns
83 T
SCH2SSH,
T
SCL2SSH
SS
 after SCK Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73
74
75, 76
77
78
79
80
79
78
SDI
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
83
Note: Refer to Figure 27-5 for load conditions.
18F8680.book Page 439 Tuesday, January 29, 2013 1:32 PM