Datasheet
2003-2013 Microchip Technology Inc. DS30491D-page 429
PIC18F6585/8585/6680/8680
TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
FIGURE 27-7: CLKO AND I/O TIMING
Param.
No.
Sym Characteristic Min Typ† Max Units Conditions
—F
OSC Oscillator Frequency Range 4 — 10 MHz HS mode
—F
SYS On-Chip VCO System Frequency 16 — 40 MHz HS mode
—t
rc
PLL Start-up Time (Lock Time) — — 2 ms
—
CLK CLKO Stability (Jitter) -2 — +2 %
† Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note: Refer to Figure 27-5 for load conditions.
OSC1
CLKO
I/O Pin
(Input)
I/O Pin
(Output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
Old Value
New Value
18F8680.book Page 429 Tuesday, January 29, 2013 1:32 PM