Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 428  2003-2013 Microchip Technology Inc.
27.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 27-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 27-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC
External CLKI Frequency
(1)
DC 40 MHz EC, ECIO, -40°C to +85°C
DC 25 MHz EC,ECIO, -40°C to +85°C, EMA
Oscillator Frequency
(1)
DC 25 MHz EC, ECIO, +85°C to +125°C
DC 16 MHz EC, ECIO, +85°C to +125°C, EMA
DC 4 MHz RC oscillator
0.1 4 MHz XT oscillator
4 25 MHz HS oscillator, -40°C to +85°C
4 25 MHz HS oscillator, -40°C to +85°C, EMA
4 25 MHz HS oscillator, +85°C to +125°C
4 16 MHz HS oscillator, +85°C to +125°C, EMA
4 10 MHz HS + PLL oscillator, -40°C to +85°C
4 6.25 MHz HS + PLL oscillator, +85°C to +125°C
DC 200 kHz LP oscillator
1T
OSC
External CLKI Period
(1)
25 — ns EC, ECIO, -40°C to +85°C
Oscillator Period
(1)
40 — ns EC,ECIO, -40°C to +85°C, EMA
40 — ns EC, ECIO, +85°C to +125°C
62.5 — ns EC, ECIO, +85°C to +125°C, EMA
250 — ns RC oscillator
250 10,000 ns XT oscillator
40 — ns HS oscillator, -40°C to +85°C
40 — ns HS oscillator, -40°C to +85°C, EMA
40 — ns HS oscillator, +85°C to +125°C
62.5 — ns HS oscillator, +85°C to +125°C, EMA
100 250 ns HS + PLL oscillator, -40°C to +85°C
160 250 ns HS + PLL oscillator, +85°C to +125°C
5 200 s LP oscillator
2T
CY Instruction Cycle Time
(1)
100
160
—
—
ns
ns
TCY = 4/FOSC, -40°C to +85°C
T
CY = 4/FOSC, +85°C to +125°C
3T
OSL,
T
OSH
External Clock in (OSC1)
High or Low Time
30
2.5
10
—
—
—
ns
s
ns
XT oscillator
LP oscillator
HS oscillator
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
—
—
—
20
50
7.5
ns
ns
ns
XT oscillator
LP oscillator
HS oscillator
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4
18F8680.book Page 428 Tuesday, January 29, 2013 1:32 PM