Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 255
PIC18F6585/8585/6680/8680
19.3 Selecting and Configuring
Automatic Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set.
When the GO/DONE
bit is set, sampling is stopped and
a conversion begins. The user is responsible for ensur-
ing the required acquisition time has passed between
selecting the desired input channel and setting the
GO/DONE
bit. This occurs when the ACQT2:ACQT0
bits (ADCON2<5:3>) remain in their Reset state (‘000’)
and is compatible with devices that do not offer
programmable acquisition times.
If desired, the ACQT bits can be set to select a pro-
grammable acquisition time for the A/D module. When
the GO/DONE
bit is set, the A/D module continues to
sample the input for the selected acquisition time, then
automatically begins a conversion. Since the acquisi-
tion time is programmed, there may be no need to wait
for an acquisition time between selecting a channel and
setting the GO/DONE
bit.
In either case, when the conversion is completed, the
GO/DONE
bit is cleared, the ADIF flag is set, and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
19.4 Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 T
AD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for T
AD:
For correct A/D conversions, the A/D conversion clock
(T
AD) must be as short as possible but greater than the
minimum T
AD (approximately 2 s, see parameter 130
for more information).
Table 19-1 shows the resultant T
AD times derived from
the device operating frequencies and the A/D clock
source selected.
19.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers con-
trol the operation of the A/D port pins. The port pins
needed as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (V
OH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES
•2 TOSC •4 TOSC
•8 TOSC • 16 TOSC
• 32 TOSC • 64 TOSC
• Internal RC Oscillator
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume current out of the device’s
specification limits.
AD Clock Source (TAD) Maximum Device Frequency
Operation ADCS2:ADCS0 PIC18FXX80/XX85 PIC18LFXX80/XX85
2 T
OSC 000 1.25 MHz 666 kHz
4 T
OSC 100 2.50 MHz 1.33 MHz
8 T
OSC 001 5.00 MHz 2.66 MHz
16 T
OSC 101 10.0 MHz 5.33 MHz
32 T
OSC 010 20.0 MHz 10.65 MHz
64 T
OSC 110 40.0 MHz 21.33 MHz
RC
(3)
x11 1.00 MHz
(1)
1.00 MHz
(2)
Note 1: The RC source has a typical TAD time of 4 s.
2: The RC source has a typical T
AD time of 6 s.
3: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D
accuracy may be out of specification.
18F8680.book Page 255 Tuesday, January 29, 2013 1:32 PM