Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 246  2003-2013 Microchip Technology Inc.
18.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RC7/RX/DT pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a synchronous master reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1 PSPIF
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 0000 000x 0000 000x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
BAUDCON
—RCIDL—SCKPBRG16— WUE ABDEN -1-0 0-00 -1-0 0-00
SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000
SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
CREN bit
RC7/RX/DT pin
RC7/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘ 0 ’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0 ’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC7/TX/CK pin
(SCKP = 0)
(SCKP = 1)
18F8680.book Page 246 Tuesday, January 29, 2013 1:32 PM