Datasheet

 2003-2013 Microchip Technology Inc. DS30491D-page 187
PIC18F6585/8585/6680/8680
16.2.9 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP1 module for PWM operation:
1. Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRISB bits.
2. Set the PWM period by loading the PR2 register.
3. Configure the ECCP1 module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
4. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
5. For Half-Bridge Output mode, set the dead-
band delay by loading ECCP1DEL<6:0> with
the appropriate value.
6. If auto-shutdown operation is required, load the
ECCPAS register:
• Select the auto-shutdown sources using the
ECCPAS<2:0> bits.
• Select the shutdown states of the PWM
output pins using PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCPAS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
7. If auto-restart operation is required, set the
PRSEN bit (ECCP1DEL<7>).
8. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
9. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMR2 overflows (TMR2IF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRISB
bits.
• Clear the ECCPASE bit (ECCP1AS<7>).
16.2.10 EFFECTS OF A RESET
Both Power-on and subsequent Resets will force all
ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
TABLE 16-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TRISE PORTE Data Direction Register 1111 1111 1111 1111
TRISG
— — —
PORTG Data Direction Register
---1 1111 ---1 1111
TMR2 Timer2 Module Register 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
ECCP1DEL PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
18F8680.book Page 187 Tuesday, January 29, 2013 1:32 PM