Datasheet

PIC18F6585/8585/6680/8680
DS30491D-page 144  2003-2013 Microchip Technology Inc.
FIGURE 10-20: RG4/P1D PIN BLOCK DIAGRAM
FIGURE 10-21: RG5/MCLR
/VPP PIN BLOCK DIAGRAM
Data Bus
WR LATG
WR TRISG
RD PORTG
Data Latch
TRIS Latch
RD TRISG
Schmitt
Trigger
Input
Buffer
I/O pin
QD
CK
QD
CK
EN
QD
EN
RD LATG
or
WR PORTG
1
0
CCP1 P1D Enable
P1D Out
Auto-Shutdown
Note: I/O pins have diode protection to VDD and VSS.
RG5/MCLR/VPP
Data Bus
RD PORTA
RD LATA
Schmitt
Trigger
MCLRE
RD TRISA
QD
EN
Latch
Filter
Low-Level
MCLR Detect
High-Voltage Detect
Internal MCLR
HV
18F8680.book Page 144 Tuesday, January 29, 2013 1:32 PM