Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 96  2003-2013 Microchip Technology Inc.
REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—CMIE— EEIE BCLIE LVDIE TMR3IE CCP2IE
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enables the write operation interrupt
0 = Disables the write operation interrupt
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enables the bus collision interrupt
0 = Disables the bus collision interrupt
bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enables the Low-Voltage Detect interrupt
0 = Disables the Low-Voltage Detect interrupt
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown