Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 54  2003-2013 Microchip Technology Inc.
CCPR3H Capture/Compare/PWM Register 3 High Byte xxxx xxxx 34, 151,
152
CCPR3L Capture/Compare/PWM Register 3 Low Byte xxxx xxxx 34, 151,
152
CCP3CON
— — DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 34, 149
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 34, 229
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 34, 223
TMR3H Timer3 Register High Byte xxxx xxxx 34, 143
TMR3L Timer3 Register Low Byte xxxx xxxx 34, 143
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 34, 143
PSPCON IBF OBF IBOV PSPMODE
— — — — 0000 ---- 34, 129
SPBRG1 USART1 Baud Rate Generator 0000 0000 34, 205
RCREG1 USART1 Receive Register 0000 0000 34, 206
TXREG1 USART1 Transmit Register 0000 0000 34, 204
TXSTA1 CSRC TX9 TXEN SYNC —BRGHTRMTTX9D0000 -010 34, 198
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 34, 199
EEADRH
— — — — — — EE Adr Register High ---- --00 34, 79
EEADR Data EEPROM Address Register 0000 0000 34, 79
EEDATA Data EEPROM Data Register 0000 0000 34, 79
EECON2 Data EEPROM Control Register 2 (not a physical register) ---- ---- 34, 79
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 34, 80
IPR3
— — RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 35, 100
PIR3
— — RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 35, 94
PIE3
— — RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 35, 97
IPR2
—CMIP— EEIP BCLIP LVDIP TMR3IP CCP2IP -1-1 1111 35, 99
PIR2
—CMIF— EEIF BCLIF LVDIF TMR3IF CCP2IF -0-0 0000 35, 93
PIE2
—CMIE— EEIE BCLIE LVDIE TMR3IE CCP2IE -0-0 0000 35, 96
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 35, 98
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 35, 92
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35, 95
MEMCON
(3)
EBDIS —WAIT1WAIT0— —WM1WM00-00 --00 35, 71
TRISJ
(3)
Data Direction Control Register for PORTJ 1111 1111 35, 125
TRISH
(3)
Data Direction Control Register for PORTH 1111 1111 35, 122
TRISG
— — — Data Direction Control Register for PORTG ---1 1111 35, 120
TRISF Data Direction Control Register for PORTF 1111 1111 35, 117
TRISE Data Direction Control Register for PORTE 1111 1111 35, 114
TRISD Data Direction Control Register for PORTD 1111 1111 35, 111
TRISC Data Direction Control Register for PORTC 1111 1111 35, 109
TRISB Data Direction Control Register for PORTB 1111 1111 35, 106
TRISA
— TRISA6
(1)
Data Direction Control Register for PORTA -111 1111 35, 103
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.