Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 53
PIC18F6520/8520/6620/8620/6720/8720
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register)
n/a 57
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register) – value of FSR2 offset by value in WREG
n/a 57
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 57
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 33, 57
STATUS
— — —NOVZDCC---x xxxx 33, 59
TMR0H Timer0 Register High Byte 0000 0000 33, 133
TMR0L Timer0 Register Low Byte xxxx xxxx 33, 133
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 33, 131
OSCCON
— — — — — — —SCS---- ---0 25, 33
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 33, 235
WDTCON
— — — — — — —SWDTE---- ---0 33, 250
RCON IPEN
— —RITO PD POR BOR 0--1 11qq 33, 60,
101
TMR1H Timer1 Register High Byte xxxx xxxx 33, 135
TMR1L Timer1 Register Low Byte xxxx xxxx 33, 135
T1CON RD16
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 33, 135
TMR2 Timer2 Register 0000 0000 33, 141
PR2 Timer2 Period Register 1111 1111 33, 142
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 33, 141
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 33, 157
SSPADD SSP Address Register in I
2
C Slave mode. SSP Baud Rate Reload Register in I
2
C Master mode. 0000 0000 33, 166
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 33, 158
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 33, 168
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 33, 169
ADRESH A/D Result Register High Byte xxxx xxxx 34, 215
ADRESL A/D Result Register Low Byte xxxx xxxx 34, 215
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 34, 213
ADCON1
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 34, 214
ADCON2 ADFM
— — — — ADCS2 ADCS1 ADCS0 0--- -000 34, 215
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 34, 151,
152
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 34, 151,
152
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 34, 149
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 34, 151,
152
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 34, 151,
152
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 34, 149
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.