Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 368  2003-2013 Microchip Technology Inc.
LFSR ........................................................................283
MOVF .......................................................................283
MOVFF ....................................................................284
MOVLB ....................................................................284
MOVLW ...................................................................285
MOVWF ...................................................................285
MULLW ....................................................................286
MULWF ....................................................................286
NEGF .......................................................................287
NOP .........................................................................287
POP .........................................................................288
PUSH .......................................................................288
RCALL .....................................................................289
RESET .....................................................................289
RETFIE ....................................................................290
RETLW ....................................................................290
RETURN ..................................................................291
RLCF ........................................................................291
RLNCF .....................................................................292
RRCF .......................................................................292
RRNCF ....................................................................293
SETF ........................................................................293
SLEEP .....................................................................294
SUBFWB ..................................................................294
SUBLW ....................................................................295
SUBWF ....................................................................295
SUBWFB ..................................................................296
SWAPF ....................................................................296
TBLRD .....................................................................297
TBLWT .....................................................................298
TSTFSZ ...................................................................299
XORLW ....................................................................299
XORWF ....................................................................300
Summary Table ........................................................262
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON Registers .............................................................89
Inter-Integrated Circuit. See I
2
C
Internet Address ...............................................................375
Interrupt Sources ..............................................................239
A/D Conversion Complete .......................................217
Capture Complete (CCP) .........................................151
Compare Complete (CCP) .......................................152
INT0 .........................................................................102
Interrupt-on-Change (RB7:RB4) ..............................106
PORTB, Interrupt-on-Change ..................................102
RB0/INT Pin, External ..............................................102
TMR0 .......................................................................102
TMR0 Overflow ........................................................133
TMR1 Overflow ................................................135, 138
TMR2 to PR2 Match ................................................142
TMR2 to PR2 Match (PWM) ............................141, 154
TMR3 Overflow ................................................143, 145
TMR4 to PR4 Match ................................................148
TMR4 to PR4 Match (PWM) ....................................147
Interrupts ............................................................................87
Control Registers .......................................................89
Enable Registers ........................................................95
Flag Registers ............................................................92
Logic ..........................................................................88
Priority Registers ........................................................98
Reset Control Registers ...........................................101
IORLW .............................................................................282
IORWF .............................................................................282
IPR Registers .....................................................................98
K
Key Features
Easy Migration ............................................................. 7
Expanded Memory ....................................................... 7
External Memory Interface ........................................... 7
Other Special Features ................................................ 7
L
LFSR ................................................................................ 283
Low-Voltage Detect ......................................................... 233
Characteristics ......................................................... 316
Converter Characteristics ........................................ 316
Effects of a Reset .................................................... 237
Operation ................................................................. 236
Current Consumption ...................................... 237
During Sleep .................................................... 237
Reference Voltage Set Point ........................... 237
Typical Application ................................................... 233
Low-Voltage ICSP Programming ..................................... 257
LVD. See Low-Voltage Detect. ........................................ 233
M
Master SSP (MSSP) Module
Overview .................................................................. 157
Master SSP I
2
C Bus Data Requirements ........................ 336
Master SSP I
2
C Bus Start/Stop Bits Requirements ......... 335
Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP
Memory Organization
Data Memory ............................................................. 47
Memory Programming Requirements .............................. 317
Microchip Internet Web Site ............................................. 375
Microcontroller Mode ......................................................... 71
Microprocessor Mode ........................................................ 71
Microprocessor with Boot Block Mode ............................... 71
Migration from High-End to Enhanced Devices ............... 363
Migration from Mid-Range to Enhanced Devices ............ 362
MOVF .............................................................................. 283
MOVFF ............................................................................ 284
MOVLB ............................................................................ 284
MOVLW ........................................................................... 285
MOVWF ........................................................................... 285
MPLAB ASM30 Assembler, Linker, Librarian .................. 302
MPLAB Integrated Development Environment Software . 301
MPLAB PM3 Device Programmer ................................... 304
MPLAB REAL ICE In-Circuit Emulator System ............... 303
MPLINK Object Linker/MPLIB Object Librarian ............... 302
MSSP ............................................................................... 157
ACK
Pulse ....................................................... 170, 171
Clock Stretching ....................................................... 176
10-bit Slave Receive Mode (SEN = 1) ............. 176
10-bit Slave Transmit Mode ............................. 176
7-bit Slave Receive Mode (SEN = 1) ............... 176
7-bit Slave Transmit Mode ............................... 176
Clock Synchronization and the CKP bit ................... 177
Control Registers (general) ...................................... 157
Enabling SPI I/O ...................................................... 161
I
2
C Mode ................................................................. 166
Acknowledge Sequence Timing ...................... 190
Baud Rate Generator ...................................... 183
Bus Collision
During a Repeated Start Condition .......... 194
Bus Collision During a Start Condition ............ 192
Bus Collision During a Stop Condition ............. 195
Clock Arbitration .............................................. 184
Effect of a Reset .............................................. 191
I
2
C Clock Rate w/BRG .................................... 183
Master Mode .................................................... 181
Reception ................................................ 187