Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 35
PIC18F6520/8520/6620/8620/6720/8720
IPR3 PIC18F6X20 PIC18F8X20 --11 1111 --11 1111 --uu uuuu
PIR3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu
PIE3 PIC18F6X20 PIC18F8X20 --00 0000 --00 0000 --uu uuuu
IPR2 PIC18F6X20 PIC18F8X20 -1-1 1111 -1-1 1111 -u-u uuuu
PIR2 PIC18F6X20 PIC18F8X20 -0-0 0000 -0-0 0000 -u-u uuuu
(1)
PIE2 PIC18F6X20 PIC18F8X20 -0-0 0000 -0-0 0000 -u-u uuuu
IPR1 PIC18F6X20 PIC18F8X20 0111 1111 0111 1111 uuuu uuuu
PIR1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu
(1)
PIE1 PIC18F6X20 PIC18F8X20 0000 0000 0000 0000 uuuu uuuu
MEMCON
PIC18F6X20 PIC18F8X20 0-00 --00 0-00 --00 u-uu --uu
TRISJ PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISH PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISG PIC18F6X20 PIC18F8X20 ---1 1111 ---1 1111 ---u uuuu
TRISF PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISE PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISD PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISC PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISB PIC18F6X20 PIC18F8X20 1111 1111 1111 1111 uuuu uuuu
TRISA
(5,6)
PIC18F6X20 PIC18F8X20 -111 1111
(5)
-111 1111
(5)
-uuu uuuu
(5)
LATJ PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATH PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATG PIC18F6X20 PIC18F8X20 ---x xxxx ---u uuuu ---u uuuu
LATF PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATE PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATD PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATC PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATB PIC18F6X20 PIC18F8X20 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5,6)
PIC18F6X20 PIC18F8X20 -xxx xxxx
(5)
-uuu uuuu
(5)
-uuu uuuu
(5)
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.