Datasheet

 2003-2013 Microchip Technology Inc. DS39609C-page 339
PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-26: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D Clock Period PIC18FXX20 1.6 20
(5)
sTOSC based, VREF  3.0V
PIC18LFXX20 3.0 20
(5)
sTOSC based, VREF full range
PIC18FXX20 2.0 6.0 s A/D RC mode
PIC18LFXX20 3.0 9.0 s A/D RC mode
131 T
CNV Conversion Time
(not including acquisition time) (Note 1)
11 12 TAD
132 TACQ Acquisition Time (Note 3) 15
10
—
—
s
s
-40C  Temp  +125C
0C  Temp  +125C
135 T
SWC Switching Time from Convert  Sample — (Note 4)
136 TAMP Amplifier Settling Time (Note 2) 1—s This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on C
HOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when
input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
DD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels
is 50.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the T
AD clock divider.