Datasheet

PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 338  2003-2013 Microchip Technology Inc.
TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXX20 (INDUSTRIAL, EXTENDED)
PIC18LFXX20 (INDUSTRIAL)
FIGURE 26-26: A/D CONVERSION TIMING
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A01 N
R Resolution — — 10 bit
A03 E
IL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.0V
A04 E
DL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.0V
A05 E
G Gain Error — — <±1 LSb VREF = VDD = 5.0V
A06 E
OFF Offset Error — — <±1.5 LSb VREF = VDD = 5.0V
A10 — Monotonicity guaranteed
(2)
—VSS  VAIN  VREF
A20
A20A
VREF Reference Voltage
(V
REFH – VREFL)
1.8V
3V
—
—
—
—
V
V
V
DD < 3.0V
V
DD  3.0V
A21 V
REFH Reference Voltage High AVSS —AVDD + 0.3V V
A22 V
REFL Reference Voltage Low AVSS – 0.3V
(5)
—VREFH V
A25 V
AIN Analog Input Voltage AVSS – 0.3V
(5)
—AVDD + 0.3V
(5)
VVDD  2.5V (Note 3)
A30 ZAIN Recommended Impedance of
Analog Voltage Source
——2.5k (Note 4)
A50 I
REF VREF Input Current (Note 1) —
—
—
—
5
150
A
A
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: Vss  V
AIN  VREF
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: For V
DD < 2.5V, VAIN should be limited to <.5 VDD.
4: Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times.
5: IV
DD – AVDDI must be <3.0V and IAVSS – VSSI must be <0.3V.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY